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Homework3Description - ECE 485/585 Fall 2009 Homework 3 1....

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ECE 485/585 Fall 2009 Homework 3 1. A memory hierarchy for a 3.2 GHz 32-bit processor employs an L1 cache with a hit time of 2 cycles and a hit rate of 90%. The L2 cache has a hit time of 10 cycles and a hit rate of 95%. L1 and L2 caches lines are 64 bytes. The L2 cache is backed by a DDR2-533 DIMM with tRCD = CL=4 using a 64-bit data bus (no ECC). Assume that an activate command is required for every cache line fill. [10] What is the average memory access time for this system assuming it does not use critical word first. [10] How much will using critical word first improve the average memory access time of this system? [10] Assuming supporting critical word first requires the same additional die area as a doubling the size of the L1 cache and that simulation shows that a doubling of the L1 cache would increase its hit time to 3 cycles and its hit rate to 95%, which alternative would you choose?
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2. [10] Consider a direct-mapped cache with only 4 lines (blocks). Each line contains one 32-bit word. The system is byte addressed on word boundaries and uses write
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This note was uploaded on 02/01/2010 for the course ECE 585 taught by Professor Faust during the Fall '08 term at Portland State.

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Homework3Description - ECE 485/585 Fall 2009 Homework 3 1....

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