Homework4Description

Homework4Description - ECE 485/585 Fall 2009 Homework 4 1....

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ECE 485/585 Fall 2009 Homework 4 1. [25] In discussing the MESI protocol we never described what happens when a cache casts out a cache line (victim) due to a conflict miss. What should happen to ensure coherence with the other caches? Describe your reasoning and approach and note any additional states or state transitions required to the MESI state transition diagram described in class.
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2. [25] For L1 and L2 caches to maintain inclusivity (that is any line in L1 must also appear in L2), any line placed into L1 must also be placed into L2. Since L2 would be the source for these lines, this is easily enough done. What is the other requirement for maintaining inclusivity? How will this affect the behavior of a snooping L2 cache?
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3. [25] A processor such as the PowerPC G3, widely deployed in earlier Apple Macintosh systems, is primarily intended for use in uniprocessor systems, and hence has a very simple MEI cache coherence protocol. (a) [5] Identify and discuss a reason why even a uniprocessor design should support
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Homework4Description - ECE 485/585 Fall 2009 Homework 4 1....

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