memory - 6.004 Memory hierarchy Fall 2009 Announcements...

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6.004 http://6004.csail.mit.edu/currentsemester/[12/1/2009 9:19:39 PM] Fall 2009 Announcements Handouts Tutorial problems Past Quizzes On-line assignments Course info Course description Course objectives Course calendar Lab hours Courseware Suggestions Suggestion Box Previous terms Lab Queue WIKI (NEW! Lab hin Memory hierarchy indicates problems that have been selected for discussion in section, time permitting. Problem 1. The following is a sequence of address references given as word addresses: 2,3,11,16,21,13,64,48,19,11,3,22,4,27,6,11 A. Show the hits and misses and final cache contents for a fully associative cache with one- word blocks and a total size of 16 words. Assume LRU replacement. 2: miss, cache now holds: 2 3: miss, cache now holds: 3, 2 11: miss, cache now holds: 11, 3, 2 16: miss, cache now holds: 16, 11, 3, 2 21: miss, cache now holds: 21, 16, 11, 3, 2 13: miss, cache now holds: 13, 21, 16, 11, 3, 2 64: miss, cache now holds: 64, 13, 21, 16, 11, 3, 2 48: miss, cache now holds: 48, 64, 13, 21, 16, 11, 3, 2 19: miss, cache now holds: 19, 48, 64, 13, 21, 16, 11, 3, 2 11: hit, cache now holds: 11, 19, 48, 64, 13, 21, 16, 3, 2 3: hit, cache now holds: 3, 11, 19, 48, 64, 13, 21, 16, 2 22: miss, cache now holds: 22, 3, 11, 19, 48, 64, 13, 21, 16, 2 4: miss, cache now holds: 4, 22, 3, 11, 19, 48, 64, 13, 21, 16, 2 27: miss, cache now holds: 27, 4, 22, 3, 11, 19, 48, 64, 13, 21, 16, 2 6: miss, cache now holds: 6, 27, 4, 22, 3, 11, 19, 48, 64, 13, 21, 16, 2 11: hit, cache now holds: 11, 6, 27, 4, 22, 3, 19, 48, 64, 13, 21, 16, 2 B. Show the hits and misses and final cache contents for a fully associative cache with four - word blocks and a total size of 16 words. Assume LRU replacement. With a N-word block of data for each cache entry, note that the N words in a cache entry will have consecutive memory addresses starting with a word address that's a multiple of N . 2: miss, cache now holds: 0-3 3: hit, cache now holds: 0-3 11: miss, cache now holds: 8-11, 0-3 16: miss, cache now holds: 16-19, 8-11, 0-3 21: miss, cache now holds: 20-23, 16-19, 8-11, 0-3 13: miss, cache now holds: 12-15, 20-23, 16-19, 8-11 64: miss, cache now holds: 64-67, 12-15, 20-23, 16-19 48: miss, cache now holds: 48-51, 64-67, 12-15, 20-23 19: miss, cache now holds: 16-19, 48-51, 64-67, 12-15 11: miss, cache now holds: 8-11, 16-19, 48-51, 64-67 3: miss, cache now holds: 0-3, 8-11, 16-19, 48-51 22: miss, cache now holds: 20-23, 0-3, 8-11, 16-19 4: miss, cache now holds: 4-7, 20-23, 0-3, 8-11
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6.004 http://6004.csail.mit.edu/currentsemester/[12/1/2009 9:19:39 PM] 27: miss, cache now holds: 24-27, 4-7, 20-23, 0-3 6: hit, cache now holds: 4-7, 24-27, 20-23, 0-3 11: miss, cache now holds: 8-11, 4-7, 24-27, 20-23 Problem 2. Cache multiple choice: A. If a cache access requires one clock cycle and handling cache misses stalls the processor for an additional five cycles, which of the following cache hit rates comes closest to achieving
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This note was uploaded on 02/01/2010 for the course ECE 585 taught by Professor Faust during the Fall '08 term at Portland State.

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memory - 6.004 Memory hierarchy Fall 2009 Announcements...

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