# hw4_09 - 2-input OR, and 2-input XOR gates. (d) Re-design...

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Department of Electrical and Computer Engineering The Johns Hopkins University 520.137 Introduction to Electrical and Computer Engineering – Fall 2009 Homework Assignment IV Reading Assignment: Kuc Chapter 4 and Kerns-Irwin Chapter 13 1. Kerns-Irwin Problem 13.18 2. Use Boolean algebra to prove the following identity ABC + AB C + A B C + A BC = A. Construct a truth table to con±rm your algebra. 3. Construct truth tables to prove the following equalities (a) A ( B + C )= AB + AC (b) ABC = A + B + C 4. Consider the design of a digital divisible-by-3 circuit which takes in as inputs a 4-bit non- negative binary number X 3 X 2 X 1 X 0 and outputs a 1 whenever the decimal equivalence of the binary input is divisible by the decimal number 3. In other words, the circuit yields a 0 output when the input in decimal is not a multiple of 3. Note that zero is considered to be divisible by 3. (a) Construct the truth table for the 4-input ( X 3 X 2 X 1 X 0 ) divisible-by-3 circuit. (b) Find the simpli±ed Boolean expression for the output Y in terms of the inputs { X 3 ,X 2 ,X 1 ,X 0 } . (c) Implement the divisible-by-3 circuit using only basic gates: INVERTER, 2-input AND,

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Unformatted text preview: 2-input OR, and 2-input XOR gates. (d) Re-design your circuit so that it now becomes a divisible-by-6 circuit. Implement your modi±ed design with basic gates. (e) What about a divisible-by-2 circuit (in other words, an even-number detection circuit)? 5. Consider the design of a multiplier which accepts two 2-bit non-negative binary numbers – A 1 A and B 1 B – as inputs and yields the 4-bit output Y 3 Y 2 Y 1 Y . Assume that the stock room has an ample supply of basic gates as well as full adders. (a) Draw the circuit that performs the partial product of B and A 1 A . How about the product of B 1 and A 1 A ? (b) Use your result in Part a to implement the multiplier. Hint: use a cascade of full adders and beware of the shift. (c) Find the logic function for Y 3 , the multiplication over±ow bit. Due date: October 16 in class...
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## This note was uploaded on 02/02/2010 for the course ENGINEERIN 520.101 taught by Professor Tracdtran during the Winter '06 term at Johns Hopkins.

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hw4_09 - 2-input OR, and 2-input XOR gates. (d) Re-design...

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