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Unformatted text preview: Department of Electrical and Computer Engineering The Johns Hopkins University 520.137 Introduction to Electrical and Computer Engineering Fall 2009 Homework Assignment V Reading Assignment: Kuc Chapter 4 and Kerns-Irwin Chapter 13 1. Consider a modified SR-FF as depicted in the figure below. Q Q S R E FF S R E Q Q (a) Sketch a typical set of timing diagrams that can demonstrate the operational behavior of the ip-op. Describe the difference between this modified SR-FF and the original one described in lecture. (b) Draw the finite state machine for the modified SR-FF. (c) Figure 1 shows another extension of the SR-FF, called the data latch . Sketch the timing diagram for the output Q of the data latch given that Q = 1 initially. FF S R E Q Q CLK D Q D CLK FF S R E Q Q CLK D Q D CLK D CLK Figure 1: The data latch. 2. Assume that you have an unlimited supply of inverters, AND gates, OR gates, and the toggle ip-ops (T-FF) where the output T responds to the falling edge of its input...
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- Winter '06