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# Day2 - ESE680-002(ESE534 Computer Organization Day 2 Logic...

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Penn ESE680-002 Spring2007 -- DeHon 1 ESE680-002 (ESE534): Computer Organization Day 2: January 10, 2007 Logic and FSM Review

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Penn ESE680-002 Spring2007 -- DeHon 2 Last Time Computational Design as an Engineering Discipline Importance of Costs
Penn ESE680-002 Spring2007 -- DeHon 3 Today Simple abstract computing building blocks gates, boolean logic registers, RTL Logic in Gates optimization properties costs Sequential Logic

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Penn ESE680-002 Spring2007 -- DeHon 4 Computer Architecture vs. Logic Design Logic Design is a mature discipline There are a set of systematic techniques to implement and optimize We can automate those techniques Nonetheless, solutions change with costs We can automate wrt a single cost Still work to do for multiple, incomparable costs
Penn ESE680-002 Spring2007 -- DeHon 5 Stateless Functions (Combinational Logic) Compute some “ function – f(i 0 ,i 1 ,…i n ) o 0 ,o 1 ,…o m Each unique input vector implies a particular, deterministic, output vector

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Penn ESE680-002 Spring2007 -- DeHon 6 Specification in Boolean logic o=a+b o=/(a*b) o=a*/b o=a*/b + b o=a*b+b*c+d*e+/b*f + f*/a+abcdef o=(a+b)(/b+c)+/b*/c
Penn ESE680-002 Spring2007 -- DeHon 7 Implementation in Gates Gate: small Boolean function Goal : assemble gates to cover our desired Boolean function Collection of gates should implement same function I.e. collection of gates and Boolean function should have same Truth Table

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Penn ESE680-002 Spring2007 -- DeHon 8 Covering with Gates o=(a+/b)(b+c)+/b*/c
Penn ESE680-002 Spring2007 -- DeHon 9 Equivalence There is a canonical specification for a Boolean function its Truth Table Two expressions, gate netlists, a gate netlist and an expression -- are the same iff. They have the same truth table

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Penn ESE680-002 Spring2007 -- DeHon 10 Netlist Netlist: collection of interconnected gates A list of all the gates and what they are connected to
Penn ESE680-002 Spring2007 -- DeHon 11 Truth Table o=/a*/b*c+/a*b*/c+a*b*/c+a*/b*c a b c o 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 0

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Penn ESE680-002 Spring2007 -- DeHon 12 How many gates? o=/a*/b*c+/a*b*/c+a*b*/c+a*/b*c a b c o 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 0
Penn ESE680-002 Spring2007 -- DeHon 13 How many gates? o=(a+/b)(b+c)+/b*/c a b c o 0 0 0 1 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1

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Penn ESE680-002 Spring2007 -- DeHon 14 Engineering Goal Minimize resources area, gates Exploit structure of logic “An Engineer can do for a dime what everyone else can do for a dollar.”
Penn ESE680-002 Spring2007 -- DeHon 15 Sum of Products o=/a*/b*c+/a*b*/c+a*b*/c+a*/b*c o=(a+b)(/b+/c) a*b+a*/c+b*/c o=(a+/b)(b+c)+/b*/c a*b+a*c+/b*c +/b*/c

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Penn ESE680-002 Spring2007 -- DeHon 16 Minimum Sum of Products o=/a*/b*c+/a*b*/c+a*b*/c+a*/b*c /b*c + b*/c
Penn ESE680-002 Spring2007 -- DeHon 17 Minimum Sum of Products o=(a+b)(/b+/c) 0 0 1 1 1 1 0 0 0 1 00 01 11 10 ab c a*/b + a*/c + b*/c a*/b + b*/c a*/b+a*/c+b*/c

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Penn ESE680-002 Spring2007 -- DeHon 18 Redundant Terms o=(a+b)(/b+/c) a*/b+ a*/c +b*/c a*/b + b*/c 0 0 1 1 1 1 0 0 0 1 00 01 11 10 ab c
Penn ESE680-002 Spring2007 -- DeHon 19 There is a Minimum Area Implementation o=(a+b)(/b+/c) a*/b+ a*/c +b*/c a*/b + b*/c 0 0 1 1 1 1 0 0 0 1 00 01 11 10 ab c

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