Day4_6up

Day4_6up - 1 Penn ESE534 Spring2010 -- DeHon 1 ESE534:...

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Unformatted text preview: 1 Penn ESE534 Spring2010 -- DeHon 1 ESE534: Computer Organization Day 4: January 27, 2010 Sequential Logic (FSMs, Pipelining, FSMD) Penn ESE534 Spring2010 -- DeHon 2 Previously Boolean Logic Gates Arithmetic Complexity of computations E.g. area and delay for addition Penn ESE534 Spring2010 -- DeHon 3 Today Sequential Logic Add registers, state Finite-State Machines (FSM) Register Transfer Level (RTL) logic Datapath Reuse Pipelining Latency and Throughput Finite-State Machines with Datapaths (FSMD) Preclass Can we solve the problem entirely using Boolean logic functions? Penn ESE534 Spring2010 -- DeHon 4 Penn ESE534 Spring2010 -- DeHon 5 Latches, Registers New element is a state element. Canonical instance is a register: remembers the last value it was given until told to change typically signaled by clock D Q > Why Registers? Penn ESE534 Spring2010 -- DeHon 6 2 Penn ESE534 Spring2010 -- DeHon 7 Reuse In general, we want to reuse our components in time not disposable logic How do we do allow guarantee disciplined reuse? To Reuse Logic Make sure all logic completed evaluation Outputs of gates are valid Meaningful to look at them Gates are finished with work and ready to be used again Make sure consumers get value Before being overwritten by new calculation (new inputs) Penn ESE534 Spring2010 -- DeHon 8 Synchronous Logic Model Data starts Inputs to circuit Registers Perform combinational (boolean) logic Outputs of logic Exit circuit Clocked into registers Given long enough clock Think about registers getting values updated by logic on each clock cycle Penn ESE534 Spring2010 -- DeHon 9 Penn ESE534 Spring2010 -- DeHon 10 Issues of Timing... many issues in detailed implementation glitches and hazards in logic timing discipline in clocking Were going to (mostly) work above that level for the most part this term. Will talk about the delay of logic between registers Watch for these details in ESE370/570 Preclass How do we build an adder for arbitrary input width? Penn ESE534 Spring2010 -- DeHon 11 Preclass What did the addition of state register(s) do for us? Penn ESE534 Spring2010 -- DeHon 12 3 Penn ESE534 Spring2010 -- DeHon 13 Added Power Process unbounded input with finite logic State is a finite (bounded) representation of whats happened before finite amount of stuff can remember to synopsize the past State allows behavior to depend on past (on context) Penn ESE534 Spring2010 -- DeHon 14 Finite-State Machine (FSM) (Finite Automata) Logic core Plus registers to hold state Penn ESE534 Spring2010 -- DeHon 15 FSM Model FSM a model of computations More powerful than Boolean logic functions Both Theoretically practically Penn ESE534 Spring2010 -- DeHon 16 Formal FSM Specification (Abstract from implementation)...
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Day4_6up - 1 Penn ESE534 Spring2010 -- DeHon 1 ESE534:...

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