hw2 - ESE534 University of Pennsylvania Department of...

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ESE534 Spring 2010 University of Pennsylvania Department of Electrical and System Engineering Computer Organization ESE534, Spring 2010 Assignment 2: Space-Time Multiply Monday, Jan. 25 Due: Monday, February 1, 12:00 pm Everyone should do all problems. We saw in lecture how to build various adders. In this problem, We’re asking you to review or develop various techniques for building multipliers. Give latency and area in terms of the operand bitwidth, w . (we’ll take asymptotic anal- ysis, or you can use symbolic constants in terms of primitive gates such as T fulladderslice , T and 2 , A and 2 , A registerbit , A mux 2 ) When asked to draw an implementation, show the w = 4 case. You may use hierarchical schematics. 1. Consider a spatial multiplier built out of simple, ripple-carry adders. (a) Show a 4 × 4 multiplier. (b) What is the area and latency for this multiplier? (function of w ) 2. Let’s consider an alternate technique that uses the same full adder bitslice as in the previous ripple-carry adder design, but which wires up the carries differently.
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