EEGR_211_Exam_2_SP04

# EEGR_211_Exam_2_SP04 - is specified by the following...

This preview shows page 1. Sign up to view the full content.

Name _______________________________ EEGR 211 Exam 2 Dr. Ladeji-Osias 4/28/04 Instructions: This is a 50 minute examination. Show all work to receive partial credit. 1. ( 2.5 points ) Design a combinational circuit whose input is a three-bit binary number. The circuit outputs a 0 if the input has two or more “1”s. Implement using logic gates. 2. ( 2.5 points ) Construct a 5 x 32 decoder using four 3 x 8 decoders with enable and a 2 x 4 decoder with enable. Use block diagrams. 3. ( 2.5 points ) A sequential circuit with two D flip-flops, A and B; and one input, x,
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: is specified by the following next-state equations: A(t+1) = AB’ + x, B(t+1) = x’. a. Draw the logic diagram of the circuit b. List the state table for the sequential circuit c. Draw the corresponding state diagram 4. ( 2.5 points ) Design a sequential circuit that transitions from 00 to 01 to 10 to 11 and repeats. Use flip-flops of your choice. 5. (Extra Credit) ( 0.5 points ) Implement F = xy + x’yz’ using a 4 x 1 MUX....
View Full Document

## This note was uploaded on 02/04/2010 for the course EEGR 211 taught by Professor Kemiladeji-osias during the Fall '06 term at Morgan.

Ask a homework question - tutors are online