Exam 2 9 am

Exam 2 9 am - a A two bit half adder b A two bit half...

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Name _______________________________ EEGR 211 (Ladeji-Osias) Exam 2 – 9 am 12/30/05 1. ROM: Design a circuit that outputs 2x 2 + 1 for x < 5 and x 2 – 14 for x >= 5, where x is a three bit binary number. Implement your design on using a truth table and the block diagram of a ROM. Indicate the size of your ROM. 2. Binary Arithmetic: Fill the table below using four-bit numbers for the binary representations listed. Decimal Signed Magnitude 1’s Complemen t 2’s Complement +5 1100 1000 3. Adders/Subtractors: Derive the truth table and logic diagram for
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Unformatted text preview: a. A two bit half adder b. A two bit half subtractor 4. Latches/Flip-flops: Derive a table describing the function of the circuit below. 5. Sequential Circuit Analysis: A sequential circuit with two D flip-flops, A and B; and one input, x, is specified by the following next-state equations: A(t+1) = A’B’+ xA, B(t+1) = AB a. Draw the logic diagram of the circuit b. List the state table for the sequential circuit c. Draw the corresponding state diagram...
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