Final_Examination

Final_Examination - Name Final Examination EEGR 211 Spring...

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Name_______________________________ Final Examination EEGR 211 – Spring 2002 Dr. Ladeji-Osias Instructions: Each student is allowed one double-sided 8.5”x11” note sheet. No other aids allowed. NO CALCULATORS. Select EIGHT questions to answer. Circle the questions you have chosen. 1. Counters Design a circuit that implements a counter with the following states: 000 010 100 101 011 111 000 … Show the next two states when the circuit is at 110. 2. General Are the following statements true or false? Explain. a) A gate is the most basic digital device. b) An R-S latch cannot be used to implement a J-K flip-flop. c) A ROM is a combinational circuit and an SRAM is a sequential circuit. d) Given a canonical sum of a function, one can deduce the canonical product, and vice-versa. e) The two’s complement of 110.01 2 is 0101.10 2 . 3. Hazards Timing hazards occur in a circuit when transient behavior of a logic circuit differs from steady-state analysis. What kinds of hazards occur in a circuit and how can they be eliminated? Eliminate any
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This note was uploaded on 02/04/2010 for the course EEGR 211 taught by Professor Kemiladeji-osias during the Fall '06 term at Morgan.

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Final_Examination - Name Final Examination EEGR 211 Spring...

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