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Unformatted text preview: 1. Sketch the output voltage as a function of time. 2. Write equations for the output voltage and current as functions of time. 2. For each of the following equations, 1) draw the corresponding CMOS circuit, 2) the equation for the pull up network, and 3) two equivalent gate symbols. Note: make these gates single stage. See example on next page. 1. Out = (A + BCD) 2. Out = (AB + AB) 3. Out = (A + B + CD) EEE425/591, ASU Lecture 01- 3 -Homework 1 – Example for page 2, Item #2 Out = (AB + CD)...
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- Fall '10
- Addition, Logic gate, NMOS logic, standard CMOS inverter