test_paper - Testing for Bridging Faults Flavius Gruian,...

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- 1 - Testing for Bridging Faults Flavius Gruian, CADLAB, IDA. Experimental results show that 40-50% of the physical defects occurring in contemporary MOS circuits can be modelled by bridging faults (BF). It has been also shown that the stuck-at fault model normally used in hardware testing cannot successfully model BFs. Several used BF models are described first in this paper. Then three approaches in handling bridging faults are presented: the logic testing is a gate level approach, making use of the circuit’s function to de- termine test vectors; recently a different technique became more and more popular, I DDQ test- ing or current supply monitoring (CSM), which tries to overcome some of the drawbacks of the logic approach; another novel method mainly applicable to CMOS circuits is the voltage detec- tors method. Finally, these techniques are compared, emphasizing each method’s advantages and disadvantages. 1.What are Bridging Faults? Bridging faults (BFs) are caused by shorts between normally unconnected signal lines (Fi- gure 1.a), [1]. This definition covers stuck-on, latch-ups and gate-oxide shorts. Depending on the technology the lines connected by a BF can have a definite value or not. Different models for BF deal with different technology related behaviour, trying to describe more accurately the phenomenon. Considering a gate level description of a design, one can distinguish between single and mul- tiple BFs (SBF and MBF) which connect two lines and respectively more then two lines. In the simplest BF model a multiple BF can be seen as several SBFs with common lines. Although masking relation may occur between these several SBFs, components of a MBF, as shown in [2] most of the MBFs are detected by tests for component SBFs, therefore most of the work done in this area is concerned only with SBFs referred further as BF. If a BF occurs between two lines already connected through a path, the fault is said to be a feedback bridging fault (FBF), otherwise the fault is referred as non-feedback bridging fault (NFBF). It is very likely that a FBF transforms a combinational circuit into a sequential one. If the number of inversions between the two shorted lines is odd then the FBF might lead to oscil- lations [2] which are hard to detect by the testing equipment. In order to realistic results in BF testing a good model is required. The simplest model used is the wired-model which is actually very realistic for some technologies (RTL, DTL, ECL) but
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- 2 - fails to model the BF in some other technologies (CMOS).There are two wired models used: wired-AND, and wired-OR in which the general Z(x,y) function from Figure 1.b. becomes in fact AND(x,y), and respectively OR(x,y). Of course Z(a,a) = a. In the voting model [3] the value of the function Z(x,y) when x y depends on the ratio of pull-down, pull-up strength at the short- ed points (Figure 1.c). The pull-down and pull-up resistance depend on the technology, the tran- sistor sizes, and the number of conducting transistors. Situations can appear when the value of Z(x,y) is indeterminate. This model describes more accurately the BF which can occur in
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test_paper - Testing for Bridging Faults Flavius Gruian,...

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