sardessai99 - Resistive Bridge Fault Modeling, Simulation...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon
Resistive Bridge Fault Modeling, Simulation and Test Generation 1 1 This research was supported by the National Science Foundation under grant MIP-9406946. This research was performed while Vijay Sar-Dessai was a M.S. student at Texas A&M University. Vijay R. Sar-Dessai Intel Corporation, FM5-64 1900 Prairie City Road Folsom CA 95630 Tel: (916) 356-1759 Fax: (916) (916) 377-1300 Email: D. M. H. Walker Dept. of Computer Science Texas A&M University College Station TX 77843-3112 Tel: (409) 862-4387 Fax: (409) 847-8578 Email: Abstract Resistive bridging faults in combinational CMOS circuits are studied in this work. Circuit-level models are abstracted to voltage behavior for use in voltage-level fault simulation and test generation. Fault simulation is done using different test sets in order to study their effectiveness. Test generation is done to detect the highest possible bridging resistance for each fault. Different test sets, power supply voltages, and fault models are studied on the ISCAS85 benchmark circuits. I. Introduction Shorts between circuit nodes are the predominant type of manufacturing defect [1]. These shorts can be of two types: intra-gate shorts between nodes within a logic gate and inter-gate or external shorts between outputs of different logic gates [2][3]. Inter-gate shorts, or bridging faults , account for about 90% of all shorts [3][4]. Thus in order to accurately estimate the quality of a chip, it is important to have a fault simulator for realistic bridging faults. It is also important to generate a test vector set that can achieve high fault coverage for bridging faults. The accuracy of a bridging fault simulator and automatic test pattern generator (ATPG) strongly depends on the accuracy of the bridging fault model [5]. A bridging fault model should not only consider the behavior of the driving gates, but should also include the driven gate behavior. This is because the logical interpretation of the voltage at the bridged nodes depends on the logical threshold of the gate to which the bridged node is connected. In reality, not only do different gates have different thresholds, but each input of a gate has a different threshold [6][7]. It is well known that the stuck-at fault model is inadequate for modeling bridging faults [8][9]. Many models have been developed for bridging faults [6][10][11] [12][13][14][15][16]. Most of these fault models assume a zero ohm bridge resistance, but several models assume a resistive bridge [3][17][18][19][20]. As shown in [1], many bridges can have significant resistance. Figure 1 shows the bridging resistance distribution fit to the data in [1]. R b is the bridging resistance and P(R b ) is the bridging resistance distribution function. Since a test for a zero-ohm bridge does not guarantee detection of a resistive bridge, ideally the fault model should be a resistive bridging fault model, instead of a zero- ohm bridging fault model. As noted in [21], since the resistive bridging fault model is only an approximation of defect behavior, we may need to use several different fault models to achieve high defect coverage.
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 2
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 10

sardessai99 - Resistive Bridge Fault Modeling, Simulation...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online