chap6_combinational_circuits

# chap6_combinational_circuits - Introduction to CMOS VLSI...

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Introduction to CMOS VLSI Design Lecture 8: Combinational Circuits David Harris Harvey Mudd College Spring 2004

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CMOS VLSI Design 8: Combinational Circuits Slide 2 Outline Bubble Pushing Compound Gates Logical Effort Example Input Ordering Asymmetric Gates Skewed Gates Best P/N ratio
CMOS VLSI Design 8: Combinational Circuits Slide 3 Example 1 module mux(input s, d0, d1, output y); assign y = s ? d1 : d0; endmodule 1) Sketch a design using AND, OR, and NOT gates.

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CMOS VLSI Design 8: Combinational Circuits Slide 4 Example 1 module mux(input s, d0, d1, output y); assign y = s ? d1 : d0; endmodule 1) Sketch a design using AND, OR, and NOT gates. D0 S D1 S Y
CMOS VLSI Design 8: Combinational Circuits Slide 5 Example 2 2) Sketch a design using NAND, NOR, and NOT gates. Assume ~S is available.

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CMOS VLSI Design 8: Combinational Circuits Slide 6 Example 2 2) Sketch a design using NAND, NOR, and NOT gates. Assume ~S is available. Y D0 S D1 S
CMOS VLSI Design 8: Combinational Circuits Slide 7 Bubble Pushing Start with network of AND / OR gates Convert to NAND / NOR + inverters Push bubbles around to simplify logic – Remember DeMorgan’s Law Y Y Y D Y (a) (b) (c) (d)

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CMOS VLSI Design 8: Combinational Circuits Slide 8 Example 3 3) Sketch a design using one compound gate and one NOT gate. Assume ~S is available.
CMOS VLSI Design 8: Combinational Circuits Slide 9 Example 3 3) Sketch a design using one compound gate and one NOT gate. Assume ~S is available. Y D0 S D1 S

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CMOS VLSI Design 8: Combinational Circuits Slide 10 Compound Gates Logical Effort of compound gates A B C D Y A B C Y A B C C A B A B C D A C B D 2 2 1 4 4 4 2 2 2 2 4 4 4 4 g A = 6/3 g B = 6/3 g C = 5/3 p = 7/3 g A = g B = g C = p = g D = Y A A Y g A = 3/3 p = 3/3 2 1 Y Y unit inverter AOI21 AOI22 A C D E Y B Y B C A D E A B C D E g A = g B = g C = g D = 2 2 2 2 2 6 6 6 6 3 p = g E = Complex AOI Y A B C  Y A B C D    Y A B C D E YA
CMOS VLSI Design 8: Combinational Circuits Slide 11 Compound Gates Logical Effort of compound gates A B C D Y A B C Y A B C C A B A B C D A C B D 2 2 1 4 4 4 2 2 2 2 4 4 4 4 g A = 6/3 g B = 6/3 g C = 5/3 p = 7/3 g A = 6/3 g B = 6/3 g C = 6/3 p = 12/3 g D = 6/3 Y A A Y g A = 3/3 p = 3/3 2 1 Y Y unit inverter AOI21 AOI22 A C D E Y B Y B C A D E A B C D E g A = 5/3 g B = 8/3 g C = 8/3 g D = 8/3 2 2 2 2 2 6 6 6 6 3 p = 16/3 g E = 8/3 Complex AOI Y A B C  Y A B C D    Y A B C D E YA

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CMOS VLSI Design 8: Combinational Circuits Slide 12 Example 4 The multiplexer has a maximum input capacitance of 16 units on each input. It must drive a load of 160 units. Estimate the delay of the NAND and compound gate designs.
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chap6_combinational_circuits - Introduction to CMOS VLSI...

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