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chapter4 - Digital Integrated Circuit Design I ECE 425/525...

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Digital Integrated Circuit Design I ECE 425/525 Chapter 4 Professor R. Daasch Depar tment of Electrical and Computer Engineering Portland State University Portland, OR 97207-0751 ([email protected]) http://ece .pdx.edu/ ~ ecex25 ©R.Daasch, Por tland State University 1 October 2008
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Chapter 4 Many CMOS designs meet the logical requirements Fe wer CMOS designs meet all requirements delay, pow er, manufacturable, reliable CMOS design can be realized meet requirements from extensive trial and error simulation Initial guesses far from final solution Improvements are slow Lower reliability and difficult to reach yield targets Design choices that require a rapid estimate What circuit topology? How may stages between flip-flops Size of transistors ©R.Daasch, Por tland State University 2 October 2008
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Chapter 4 A simple delay model addresses these and other questions Are all gates different, the delay model says no Does every design decision need spice, the delay model says no Can the decision be technology independent, the delay model says most of the time Delay models delay = parasitic delay + stage delay Stage delay How much current can this gate deliver to the load compared to a predetermined base (typically an inverter) What is the fanout of the gate output Parasitic delay ©R.Daasch, Por tland State University 3 October 2008
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Chapter 4 What would be the delay without an exter nal load Parasitic delay — aka internal delay is the internal delays of the (primar ily) diffusion capacitance Logical effor t is the ratio of the input capacitance to inverter with the drive same current Major contributions to RC delay are Gate delay — transistor sizing, circuit topology Interconnect — wiring Delay estimates are particular ly impor tant for the critical path RC time constant first level delay estimate Effective estimates early in design means improvements are str uctured for efficient design intervals ©R.Daasch, Por tland State University 4 October 2008
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Chapter 4 Estimates are not for perfection but for reliability Good estimates get 80%-90% of the final detailed solution Common to expend design effor t (and time) on small corrections when the overall solution is still unknown R eff is the equivalent replacement of the average current through FET Such an estimate is accurate for only a brief moment in the logic transition C eff is the nominal load such that the transition time R eff C eff = t plh + t phl 2 Contr ibutions to C Diffusion — drain terminal of transistor at output of gate (ie parasitic delay) ©R.Daasch, Por tland State University 5 October 2008
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Chapter 4 Gate oxide — gate terminals of transistors controlled by output of gate (ie logical effor t) Interconnect — the wire, metal, poly, contacts, vias linking drain to gate Contr ibutions to R Ser ies transistor networ k — effective increases L of combined logic transistor Parallel transistor networ k — effective increase of W of combined logic transistor Naturally propagation delay accumulates from gate to circuit, circuit to the system
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