chapter4 - Digital Integrated Circuit Design I ECE 425/525...

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Digital Integrated Circuit Design I ECE 425/525 Chapter 4 Professor R. Daasch Depar tment of Electrical and Computer Engineering Portland State University Portland, OR 97207-0751 (daasch@ece.pdx.edu) http://ece .pdx.edu/ ~ ecex25 ©R.Daasch, Por tland State University 1 October 2008
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Chapter 4 ManyCMOS designs meet the logical requirements Fe wer CMOS designs meet all requirements delay, pow er, manufacturable ,reliable CMOS design can be realized meet requirements from extensivetrial and error simulation Initial guesses far from final solution Improvements are slow Lowerreliability and difficult to reach yield targets Design choices that require a rapid estimate What circuit topology? Howmay stages between flip-flops Sizeoftransistors ©R.Daasch, Por tland State University 2
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Chapter 4 Asimple delaymodel addresses these and other questions Are all gates different, the delaymodel says no Does every design decision need spice ,the delaymodel says no Can the decision be technology independent, the delay model says most of the time Delaymodels delay = parasitic delay + stage delay Stage delay •H ow much current can this gate deliver to the load compared to a predetermined base (typically an inverter) •W hat is the fanout of the gate output Parasitic delay
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Chapter 4 •W hat would be the delaywithout an exter nal load •P arasitic delay—aka internal delayisthe internal delays of the (primar ily) diffusion capacitance Logical effor t is the ratio of the input capacitance to inverter with the drivesame current Major contributions to RC delayare Gate delay—transistor sizing, circuit topology Interconnect — wiring Delayestimates are particular ly impor tant forthe critical path RC time constant first leve ldelayestimate Effectiveestimates early in design means improvements are str uctured forefficient design intervals
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Chapter 4 Estimates are not for perfection but for reliability Good estimates get 80%-90% of the final detailed solution Common to expend design effor t (and time) on small corrections when the overall solution is still unknown R eff is the equivalent replacement of the average current through FET Such an estimate is accurate for only a brief moment in the logic transition C eff is the nominal load such that the transition time R eff C eff = t plh + t phl 2 Contr ibutions to C Diffusion — drain terminal of transistor at output of gate (ie parasitic delay) ©R.Daasch, Por tland State University 5 October 2008
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Chapter 4 Gate oxide — gate terminals of transistors controlled by output of gate (ie logical effor t) Interconnect — the wire ,metal, poly ,contacts ,vias linking drain to gate Contr ibutions to R Ser ies transistor networ k—effectiveincreases L of combined logic transistor Parallel transistor networ k—effectiveincrease of W
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This note was uploaded on 02/05/2010 for the course ECE 525 taught by Professor Daasch during the Fall '08 term at Portland State.

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chapter4 - Digital Integrated Circuit Design I ECE 425/525...

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