ELEC2607W97 - DUUIXLJIL 1 ID U-JLLJJ ll 2C 3 CARLETON...

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Unformatted text preview: DUUIXLJIL 1 ID U-JLLJJ ll: 2C] 3:! CARLETON UNIVERSITY Final rev EXAMINATION Number Name April 1 997 DURATION: 3 HOURS No. of Student: 210 Department Name a Course Number: Electronic Engineering 97.267 Course Instructor(S) Tom Ray and John Knight AUTHOFUZED MEMORANDA Any books or notes; any non—communicating calculator. Proclors please give booklets on request; please check in comer for each booklet given. Students MUST count the number of pages in this examination question paper before beginning to write, and report any discrepancy immediately to a proctor. This questlon paper has 5 pages. This examination pap- MAY NOT be taken from the examlnation room. Marks will be deducted for massive copying of non-applicable statements from the notes. (Please answer on question paper. Check [El on the right, if answer is in booklet.) 1 Short Questions a) Find an algebraic expression for P which requires 1 a) sec 4% minimum logic. Blanks are zeros. "d"s are don’t care. booklet Him: There are two minimum 2 of“ solutions with 7 [errant on rhs. (4 gates. l0 [ti-pun). b) .Find an algebraic expression for F which requires minimum logic. F is shown on two dif- f - .. ., , l b) See erent type of S—vanable maps. Blanks are zeros. d s are don 1 care book] I E El .6“ plane of map of F E plane of map of F Min .mtutt‘mr has 9 [CHE-F.“ (4 gala-5, 9 inputs). Haffmarks ffno circles berwecn layers. Fl of}: grve: 6 Jern'rj [4 garm, 9 inputs} C) DRAW the CIRCUIT to produce F and G for the two-output function below. 1 j - Minimize the total logic. “:66 Blanks are zeros. “d"s are don't care boo 13‘ El 00 01 11 6111198 Carleton University Electronic Eigincering 94.267 d) Prove or disprove that X=Y. This is a very short question, but long by some approaches. x =1(A+B)-(C)] +[fi-(fi-C +E)] + F-§+E Y = [K-§+ CJ-[B + (D+E)-E} + (F+‘G')~E e) It is easiest to analyize circuits with ANDs and OR gates with all inversions done on single let- . l e) See lens at inputs. ’ ‘ ' booklet However circuits are Implemented with NANDs, NORs (i) Convert the circuit below to use only ANDs, and ORs. D Inverting circles are only allowed at the primary inputs, that is A. B, C, D and E. Use the dotted outlines as guidelines to draw your circuit.. _F.. i. 9, 0 Given the sum of products form of a function F, find the product of sums form. 1 D See 5'? F = A<E + K-B + C-E " ‘ B00 01 11 1o bog“ D 1 g) Add circuitry to the 4—bit binary counter given. to construct a circuit which gives a “1" output: 1 S 5% - On the 61h clock pulse after coming out of reset. 9 e8 I Every 8 clock pulses thereafter. ' booDklet least 3! : a! clock reset «9 6/1/93 page 2. of '5 Carleton University Elect-unit: Engineering 94.267 h) In the PAL below: I h) See (i) Write the input letters for each AND term in front of the AND gate (the topmost one is done booklet for you). . (ii) Identify the single-variable—change hazards by wrifing sentences of the form - E] Output Z has a static- (0 or I) hazard in input E when EG,H = 1,0_1. Output __~hasra static— hazard in input _when - _I_s ._ _.- _- _- Output has a static- __ha.za.rd in input when _ Output has a static— hazard in input when _ (iii) Change the PAL program to mask the hazards. 4_,_ _..._v_)—' v._’___ _;_y_- "ms—«am M... .0.» @Efisaflam; 2 State Graph to Timing Diagram 9% Complete the timing diagram for the state graph. Show the present state and the output 2. FI=OD I If [=0 =9 2: [1:1 = z: 9611/98 page 3,0f 5 mm 333i" Carleton University Electronic Engineering 94.267 .4 3 Synchronous Machine Implementation 3) S ‘ CC ' Design a machine with minimum logic to implement the following state graph. bookle‘ The state table, state equations and circuit are expected. I: Do not change the state assignment or the operation of the machine.. ‘ 1:1 or 0 Note: reset sends the machine to state R without waiting for the clock. 1 D 1 00 01 1 1 10 o 1 o 1 00 00 "A p 01 01 l 1 1 I 10 10 4 State Reduction 4) See 16% Find what states could be made equivalent. booklet Then make a new state table with a minimum number of states. D Next State Output X=0 Z Next State . x=o x=1 9 611193 Pass 4‘ MI, 5 Cllfclon Univmity Electronic Engineering 94.267 5 Design of Synchronous Machine 5) Sec booklet The output 2 = the input X as it was at the last clock edge, until an input 1 appears D on two consecutive clock edges. (Edges 3 and 4) CL After two consecutive input ones, The dutput Z = the inverse of the input X as sampled on the last clock ‘ l ' Draw the state graph for the following machine. x edge.(Edges 5. 6, 7. 8. and 9) CLK (I) E Q 6 Hazards - 6 ) See _ , _ _ _ booklet (1)Fmd the two static and the three dynamic hazards in F = (b + E b)(a + c a)(c + c a) I: Hint; one of the static hazards may look rather dy— ! ' namic. You have to go back to the meaning of stat- ic-l and static-0 to classify it. List the hazards stating: The type of hazard The variable that changes. The values of the other variables. \ i w i R ® 611/98 pages.uf5 ...
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This note was uploaded on 02/07/2010 for the course ELEC 2607 taught by Professor Lee during the Winter '10 term at Carleton CA.

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ELEC2607W97 - DUUIXLJIL 1 ID U-JLLJJ ll 2C 3 CARLETON...

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