Lecture25-26 may 14 - ‫۴‐ ﺍﻟﻜﺘﺮﻭﻧﻴﻚ...

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Unformatted text preview: ‫۴‐ ﺍﻟﻜﺘﺮﻭﻧﻴﻚ ﻭ ﺳﻴﺴﺘﻢﻫﺎﻱ ﺩﻳﺠﻴﺘﺎﻝ‬ ‫۴‐۱‐ ﻣﻘﺪﻣﻪ‬ ‫• ﺩﺭ ﺳﻴﺴﺘﻢﻫﺎﻱ ﺩﻳﺠﻴﺘﺎﻝ ﻣﻌﻤﻮﻻ ﺳﻴﮕﻨﺎﻟﻬﺎ ﺩﻭ ﺍﺭﺯﺷﻲ ﻣﻲﺑﺎﺷﻨﺪ‪High , Low‬‬ ‫ﹰ‬ ‫• ﺩﻭ ﺣﺎﻟﺖ ‪ High‬ﻭ ‪ Low‬ﻣﺘﻨﺎﻇﺮ ﺑﺎ ﺩﻭ ﺣﺎﻟﺖ 1=‪ True‬ﻭ 0=‪ False‬ﺩﺭ ﺟﺒﺮ ﺑﻮﻝ ﻣﻲﺑﺎﺷﻨﺪ )ﺍﻟﺒﺘﻪ ﺩﺭ “ﻣﻨﻄﻖ‬ ‫ﻣﻨﻔـﻲ” ﻭﻟﺘﺎﮊ ‪ High‬ﻣﺘﻨﺎﻇﺮ ﺑﺎ ‪ Flase‬ﻭ ﻭﻟﺘﺎﮊ ‪ Low‬ﻣﺘﻨﺎﻇﺮ ﺑﺎ ‪ True‬ﻣﻲﺑﺎﺷﺪ(‬ ‫• ﺑـﺎ ﺗﻮﺟﻪ ﺑﻪ ﺍﻳﻨﻜﻪ ﺩﺭ ﺳﻴﺴﺘﻢﻫﺎﻱ ﺩﻳﺠﻴﺘﺎﻟﻲ ﺍﻟﻜﺘﺮﻭﻧﻴﻜﻲ، ﻭﻟﺘﺎﮊﻫــــﺎﻱ ﻣﺘﻨﺎﻇﺮ ﺑﺎ ﻫﺮﻳﻚ ﺍﺯ ﺩﻭ ﺣﺎﻟﺖ ‪ High‬ﻭ‬ ‫‪Low‬ﻣﻲﺗﻮﺍﻧﻨﺪ ﺩﺭ ﻳﻚ ﻣﺤﺪﻭﺩﻩ ﻣﺸﺨﺺ ﻗﺮﺍﺭ ﺩﺍﺷﺘﻪ ﺑﺎﺷﻨﺪ، ﺍﺯ ﺍﻳﻦ ﺭﻭ ﺑﻬﻨﮕﺎﻡ ﺻﺤﺒﺖ ﺩﺭ ﻣﻮﺭﺩ ﻭﻟﺘﺎﮊﻫﺎ، ﺍﻏﻠﺐ ﺍﺯ‬ ‫ﺍﻟﻔﺎﻅ ‪ High‬ﻭ ‪ Low‬ﺍﺳﺘﻔﺎﺩﻩ ﻣﻲﺷﻮﺩ )ﺗﺎ ﺍﺯ1=‪ True‬ﻭ0=‪( False‬‬ ‫ ﺑﺮﺍﻱ ﻣﺜﺎﻝ ﺩﺭ ﺧﺎﻧﻮﺍﺩﻩ‪ TTL‬ﻫﺎ )‪ (Transistor – Transistor Logic‬ﻛﻪ ﺩﺭ ﺳﺎﺧﺘﻤﺎﻥ ﺩﺍﺧﻠﻲ ﺁﻧﻬﺎ ﺍﺯ‬‫‪BJT‬ﻫﺎ ﺍﺳﺘﻔﺎﺩﻩ ﻣﻲﺷﻮﺩ:‬ ‫ﺷﺮﺍﻳﻂ ﺑﺮﺍﻱ ﺧﺮﻭﺟﻲ ‪TTL‬‬ ‫)ﺗﻮﻟﻴﺪ ﻛﻨﻨﺪﻩ(‬ ‫5.5 < ‪2 .4V < VHigh‬‬ ‫&‬ ‫‪− 0.5V ≤ VLow ≤ 0.4V‬‬ ‫ﺩﺭ ﻋﻤﻞ ﻣﻌﻤﻮﻻ ‪ Vlow ~ 0.2V‬ﻭ ‪ VHigh ~ 3.4V‬ﻣﻲﺑﺎﺷﺪ. ﺑﺎﺯﻩ ﻓﻮﻕ ﺑﻴﺸﺘﺮ ﺟﻬﺖ ﻣﻘﺎﺑﻠﻪ ﺑﺎ ﺗﻐﻴﻴﺮﺍﺕ ﺩﻣﺎ،‬ ‫ﹰ‬ ‫ﺗﻐﻴﻴﺮﺍﺕ ﻭﻟﺘﺎﮊ ﻣﻨﺒﻊ ﺗﻐﺬﻳﻪ، ﻋﺪﻡ ﻳﻜﻨﻮﺍﺧﺘﻲ ﺩﺭ ﻓﺮﺁﻳﻨﺪ ﺳﺎﺧﺖ ﺩﺭﻧﻈﺮ ﮔﺮﻓﺘﻪ ﺷﺪﻩﺍﺳﺖ. ﺍﺯ ﻃﺮﻓﻲ ﺟﻬﺖ ﻣﻘﺎﺑﻠﻪ‬ ‫ﺑﺎ ﻧﻮﻳﺰ، ‪ TTL‬ﻫﺎ ﺑﺎﻳﺪ ﺑﻨﺤﻮﻱ ﻃﺮﺍﺣﻲ ﻭ ﺳﺎﺧﺘﻪ ﺷﻮﻧﺪ ﻛﻪ ﻋﻤﻠﻜﺮﺩﻱ ﺻﺤﻴﺢ ﺩﺭ ﺍﺯﺍﺀ ‪ 0.4V‬ﻧﻮﻳﺰ ﺭﺍ ﺣﻔﻆ‬ ‫ﻧﻤﺎﻳﻨﺪ. ﺑﻌﺒﺎﺭﺗﻲ ﺍﻧﺘﻈﺎﺭ ﻣﻲﺭﻭﺩ ﻛﻪ ﻳﻚ ‪ IC‬ﺍﺯ ﻧﻮﻉ ‪ TTL‬ﻫﺮ ﻭﻟﺘﺎﮊﻱ ﺩﺭ ﻣﺤﺪﻭﺩﻩ ‪− 0.5 < VLow < 0.8V‬‬ ‫ﺭﺍ ﺑﻌﻨﻮﺍﻥ ‪ Low‬ﻭ ﻫﺮ ﻭﻟﺘﺎﮊﻱ ‪VHigh>2V‬ﺭﺍ ﺑﻌﻨﻮﺍﻥ ‪ High‬ﺗﻌﺒﻴﺮ ﻧﻤﺎﻳﺪ.‬ ‫ﺷﺮﺍﻳﻂ ﺑﺮﺍﻱ ﻭﺭﻭﺩﻱ ‪) TTL‬ﻣﺼﺮﻑ ﻛﻨﻨﺪﻩ(‬ ‫ ﺍﺯ ﻃﺮﻓﻲ ﺩﺭ “ﻣﻨﻄﻖ ﻣﻨﻔﻲ” )‪ TRUE (negative Logic‬ﺑﻮﺩﻥ ﻳﻚ ﺣﺎﻟﺖ، ﻣﺘﻨﺎﻇﺮ ﺑﺎ ﻭﻟﺘﺎﮊﻱ ‪Low‬‬‫ﺑﻮﺩﻩ ﻭ ‪ FALSE‬ﺑﻮﺩﻥ ﺣﺎﻟﺖ، ﻣﺘﻨﺎﻇﺮ ﺑﺎ ﻭﻟﺘﺎﮊﻱ ‪ High‬ﻣﻲﺑﺎﺷﺪ. ﺑﺮﺍﻱ‬ ‫ﻣﺜﺎﻝ ﺩﺭ ﺷﻜﻞ ﻣﻘﺎﺑﻞ‬ ‫5+‬ ‫‪Switch − Closed : True ( SC ) ⇒ Vout = V Low‬‬ ‫‪Switch − Closed : False ( SC ) ⇒ Vout = V High‬‬ ‫ﺑﻪ ﺍﻳﻨﮕﻮﻧﻪ ﺳﻴﮕﻨﺎﻟﻬﺎ "‪ “negative True‬ﻳﺎ "‪ “Low True‬ﮔﻔﺘﻪ ﻣﻲﺷﻮﺩ. ﺳﻴﮕﻨﺎﻟﻬﺎﻳﻲ ﻛﻪ ﺩﺭ ﺁﻧﻬﺎ‬ ‫‪TRUE‬ﺑﻮﺩﻥ ﻣﺘﻨﺎﻇﺮ ﺑﺎ ﻭﻟﺘـــﺎﮊ ‪ High‬ﺑﺎﺷﺪ "‪ “positive True‬ﮔﻔﺘﻪ ﻣﻲﺷﻮﺩ.‬ ‫‪SC‬‬ ‫‪Vout‬‬ ‫ﮔﺬﺍﺷﺘﻦ ﻳﻚ ﺧﻂ ﺗﻴﺮﻩ ﺑﺮ ﺭﻭﻱ ﻳﻚ ﺳﻴﮕﻨﺎﻝ )ﻳﺎ ﻣﺘﻐﻴﺮ ‪ (Boolean‬ﺑﻪ ﻣﻔﻬﻮﻡ ﻃﺒﻴﻌﺖ ﺳﻴﮕﻨﺎﻝ ﻣﺰﺑﻮﺭ ﺍﺯ‬ ‫ﻣﻨﻄﻖ ﻣﻨﻔﻲ ﻣﻲﺎﺷﺪ.‬ ‫• ﺩﺭ ﺳﻴﺴﺘﻢﻫـــﺎﻱ ﻛﻨﺘﺮﻝ ﺻﻨﻌﺘﻲ ﻭ ﻭﺍﺣﺪﻫﺎﻱ ﻣﻨﻄﻘﻲ ‪ (Relay Ladder Logic) Ladder‬ﺍﺯ ﺳﻮﺋﻴﭻﻫﺎ ﻳﺎ‬ ‫ﻛﻨﺘﺎﻛﺖﻫﺎﻱ "‪ “Normally Closed‬ﺑﺮﺍﻱ ﻣﻨﻄﻖ ﻣﻨﻔﻲ ﺍﺳﺘﻔﺎﺩﻩ ﻣﻲﺷﻮﺩ.‬ ‫‪C‬‬ ‫1-‪1CR‬‬ ‫‪2CR‬‬ ‫‪Contact # for 1CR‬‬ ‫‪Relay‬‬ ‫‪Contact‬‬ ‫‪2CR = 1CR AND C‬‬ ‫‪1CR‬‬ ‫# ‪Relay‬‬ ‫‪Relay‬‬ ‫‪B‬‬ ‫‪A‬‬ ‫# ‪Relay‬‬ ‫‪Coil‬‬ ‫‪1CR = A AND B‬‬ ‫ﻛﻨﺘﺎﻛﺖ ﻭ ﻳﺎ ﺳﻮﺋﻴﭻﻫﺎﻱ ‪ (normally closed) NC‬ﺩﺭ ﺻﻮﺭﺕ ﺗﺤﺮﻳﻚ ﺑﺼﻮﺭﺕ ﻣﺪﺍﺭ ﺑــﺎﺯ )‪ (False‬ﻋﻤﻞ‬ ‫ﻣﻲﻧﻤــﺎﻳﻨﺪ‬ ‫ﻛﻨﺘﺎﻛﺖ ﻭ ﻳﺎ ﺳﻮﺋﻴﭻﻫﺎﻱ ‪ (normally open) NO‬ﺩﺭ ﺻﻮﺭﺕ ﺗﺤﺮﻳﻚ ﺑﺼـﻮﺭﺕ ﻣﺪﺍﺭ ﺑﺴﺘﻪ )‪ (True‬ﻋﻤﻞ‬ ‫ﻣﻲﻧﻤﺎﻳﻨﺪ.‬ ‫• ﺩﺭ ﺳﻴﺴﺘﻢﻫــﺎﻱ ﺩﻳﺠﻴﺘـــﺎﻝ ﺑﺮﺍﻱ ﻧﻤﺎﻳﺶ ﻛﻤﻴﺖﻫﺎﻱ ﭼﻨﺪ ﺍﺭﺯﺷﻲ، ﻣﻌﻤﻮﻻ ﺍﺯ ﭼﻨﺪﻳﻦ ﺳﻴﮕﻨﺎﻝ ﺩﻭ ﺍﺭﺯﺷـﻲ‬ ‫ﹰ‬ ‫ﺍﺳﺘﻔﺎﺩﻩ ﻣﻲﺷﻮﺩ. ﺍﻣﺎ ﺩﺭ ﻫﺮ ﺣﺎﻟﺖ ﺑﺮﺧﻼﻑ ﺳﻴﺴﺘﻢﻫﺎﻱ ﺁﻧﺎﻟﻮﮒ ﻛـﻪ ﺩﺭ ﺁﻧﻬـﺎ ﻛﻤﻴـﺖﻫـﺎ ﺑﻄـﻮﺭ ﭘﻴﻮﺳـﺘﻪ )ﺑـﻴﻦ‬ ‫ﻣﻘﺎﺩﻳﺮ ﺣﺪﺍﻗﻞ ﻭ ﺣﺪﺍﻛﺜﺮ( ﺗﻐﻴﻴﺮ ﻣﻲﻧﻤﺎﻳﻨﺪ، ﺩﺭ ﺳﻴﺴﺘﻢﻫﺎﻱ ﺩﻳﺠﻴﺘـﺎﻝ ﻫـﺮ ﻛﻤﻴـــﺖ ﺩﺍﺭﺍﻱ ﺗﻌـﺪﺍﺩ ﻣﺸﺨﺼـﻲ‬ ‫ﺍﺭﺯﺵ )‪ (discrete number values‬ﺑﻴﺶ ﻧﻴﺴﺖ. ﺣـﺪﺍﻛﺜﺮ ﺗﻌـﺪﺍﺩ ﺍﺭﺯﺵﻫــﺎﻱ ﻗﺎﺑـﻞ ﻧﻤـﺎﻳﺶﺗﻮﺳـﻂ ‪n‬‬ ‫ﺳﻴﮕﻨﺎﻝ ﺩﻳﺠﻴﺘﺎﻝ ‪ 2n‬ﻣﻲﺑﺎﺷﺪ. ﺍﻣﺎ ﺑﺴﺘﮕﻲ ﺑﻪ ﻧﺤﻮﻩ ﻛﺎﺭﺑﺮﺩ ﻣﻤﻜﻦ ﺍﺳﺖ ﺗﻌـﺪﺍﺩ ﺍﺭﺯﺵﻫﺎﻱ ﻗﺎﺑﻞ ﻧﻤﺎﻳﺶ ﺑـﺎ ‪n‬‬ ‫ﺳﻴﮕﻨﺎﻝ ﻛﻤﺘﺮ ﺍﺯ ‪2n‬ﺑﺎﺷﺪ ﺑﺮﺍﻱ ﻣﺜﺎﻝ:‬ ‫٣ﺳﻴﮕﻨﺎل ‪A ، B ، C‬‬ ‫4 ارزش‬ ‫‪High‬‬ ‫.‪O.K‬‬ ‫‪Low‬‬ ‫‪Very Low‬‬ ‫‪C‬‬ ‫‪ON‬‬ ‫‪ON‬‬ ‫‪ON‬‬ ‫‪OFF‬‬ ‫‪B‬‬ ‫‪ON‬‬ ‫‪ON‬‬ ‫‪OFF‬‬ ‫‪OFF‬‬ ‫‪A‬‬ ‫‪ON‬‬ ‫‪OFF‬‬ ‫‪OFF‬‬ ‫‪OFF‬‬ ‫‪Lamps or Valves‬‬ ‫‪High‬‬ ‫.‪O.K‬‬ ‫‪Low‬‬ ‫‪Very Low‬‬ ‫‪Logic‬‬ ‫‪A‬‬ ‫‪B‬‬ ‫‪C‬‬ ‫ﺍﻟﺒﺘﻪ ﺩﺭ ﺳﻴﺴﺘﻢ ﻧﺸﺎﻥ ﺩﺍﺩﻩ ﺷـﺪﻩ ٤ ﺗﺮﻛﻴﺐ ﺩﻳﮕﺮ ﺑﺮﺍﻱ ﺳﻮﺋﻴﭻﻫﺎﻱ ‪ A‬ﻭ ‪ B‬ﻭ ‪ C‬ﻭﺟﻮﺩ ﺩﺍﺭﺩ ﻛﻪ ﻧﻤﺎﻳﺎﻧﮕﺮ‬ ‫‪Failure‬ﻳﺎ ﺧﺮﺍﺑﻲ ﺑﺮﺍﻱ ﻳﻚ ﻳﺎ ﭼﻨﺪ ﺳﻮﺋﻴﭻ ﻣﺤﺴﻮﺏ ﻣﻲﺷﻮﺩ )ﻣﺎﻧﻨﺪ‪( A:ON B:OFF C:OFF‬‬ ‫•ﻣﺪﺍﺭﻫﺎﻱ ﺩﻳﺠﻴﺘﺎﻟﻲ ﺭﺍ ﻣﻲﺗﻮﺍﻥ ﺑﻪ ﺳﻪ ﻧﻮﻉ ﺯﻳﺮ ﺗﻘﺴﻴﻢ ﻧﻤﻮﺩ:‬ ‫ﻣﺪﺍﺭﻫﺎﻱ ﻣﻨﻄﻘﻲ ﺗﺮﻛﻴﺒﻲ)‪(Combinational Logic‬‬‫ﺍﻳﻨﮕﻮﻧﻪ ﻣﺪﺍﺭﻫﺎ ﺩﺍﺭﺍﻱ ﭼﻨﺪﻳﻦ ﻭﺭﻭﺩﻱ ﺩﻳﺠﻴﺘﺎﻝ ﻭ ﻳﻚ ﻳﺎ ﭼﻨﺪ ﺧﺮﻭﺟﻲ ﺩﻳﺠﻴﺘﺎﻝ ﻣﻲﺑﺎﺷﻨﺪ. ﻭﺿﻌﻴﺖ ﺧﺮﻭﺟـﻲﻫـﺎ‬ ‫ﺑﺼﻮﺭﺕ ﻣﻨﺤﺼﺮ ﺑﻔﺮﺩﻱ ﺑﻪ ﻭﺿﻌﻴﺖ ﻳﺎ ﺗﺮﻛﻴﺐ ﻭﺭﻭﺩﻱﻫﺎ ﺑﺴـﺘﮕﻲ ﺩﺍﺷـﺘﻪ ﻭ ﺑﻌﺒــﺎﺭﺗﻲ ﻳـﻚ ﺗــﺮﻛﻴﺐ ﻣﺸـﺨﺺ ﺍﺯ‬ ‫ﻭﺭﻭﺩﻱﻫﺎ ﻫﻤﻮﺍﺭﻩ ﺑﻪ ﻳﻚ ﻭﺿﻌﻴﺖ ﻳﺎ ﺗـﺮﻛﻴﺐ ﺧﺎﺻﻲ ﺍﺯ ﺧﺮﻭﺟﻲﻫــﺎ ﻣﻨﺠــــﺮ ﻣﻲﮔﺮﺩﺩ .‬ ‫ﻣﺜﺎﻝ:‬ ‫2‪V‬‬ ‫2‪V‬‬ ‫‪Fault‬‬ ‫1‪V‬‬ ‫1‪V‬‬ ‫‪Logic‬‬ ‫‪A‬‬ ‫‪B‬‬ ‫‪C‬‬ ‫ﻭﺭﻭﺩﻱﻫﺎ‬ ‫ﺧﺮﻭﺟﻲﻫﺎ‬ ‫‪Fault‬‬ ‫ﻫﺮ ﺩﻭ ﺷﻴﺮ ﺑﺎﺯ‬ ‫ﺷﻴﺮ 2‪ V‬ﺑﺎﺯ‬ ‫ﺷﻴﺮ ﺑﺎﺯ 1‪V‬‬ ‫ﻫﺮ ﺩﻭ ﺷﻴﺮ ﺑﺴﺘﻪ‬ ‫2‪V‬‬ ‫1‪V‬‬ ‫‪C‬‬ ‫‪B‬‬ ‫‪A‬‬ ‫‪Condition‬‬ ‫0‬ ‫0‬ ‫1‬ ‫0‬ ‫1‬ ‫1‬ ‫1‬ ‫0‬ ‫1‬ ‫1‬ ‫0‬ ‫0‬ ‫0‬ ‫0‬ ‫0‬ ‫0‬ ‫1‬ ‫0‬ ‫0‬ ‫1‬ ‫0‬ ‫0‬ ‫0‬ ‫0‬ ‫0‬ ‫1‬ ‫0‬ ‫1‬ ‫0‬ ‫1‬ ‫0‬ ‫1‬ ‫0‬ ‫0‬ ‫1‬ ‫1‬ ‫0‬ ‫0‬ ‫1‬ ‫1‬ ‫0‬ ‫0‬ ‫0‬ ‫0‬ ‫1‬ ‫1‬ ‫1‬ ‫1‬ ‫‪Very low‬‬ ‫‪Low‬‬ ‫‪Fault‬‬ ‫.‪o.k‬‬ ‫‪Fault‬‬ ‫‪Fault‬‬ ‫‪Fault‬‬ ‫‪High‬‬ ‫ﻣﺪﺍﺭﻫﺎﻱ ﻣﻨﻄﻘﻲ ﺗﺮﺗﻴﺒﻲ)‪(Sequential Logic‬‬‫ﺩﺭ ﺍﻳﻨﮕﻮﻧﻪ ﻣﺪﺍﺭﻫﺎ، ﺧﺮﻭﺟﻲﻫﺎ ﺿﻤﻦ ﺍﻳﻨﻜﻪ ﺑﻪ ﻭﺭﻭﺩﻱﻫﺎ ﺑﺴﺘﮕﻲ ﺩﺍﺭﻧﺪ ﺑﻠﻜﻪ ﺗﺮﺗﻴﺐ ﺗﻐﻴﻴﺮﺍﺕ ﻭﺭﻭﺩﻱﻫﺎ ﻭ ﻋﻤﻠﻜﺮﺩ ﻗﺒﻠﻲ‬ ‫ﺳﻴﺴﺘﻢ ﻧﻴﺰ ﺩﺭ ﻣﻘﺎﺩﻳﺮ ﺧﺮﻭﺟﻲ ﻣﺆﺛﺮ ﻣﻲﺑﺎﺷﺪ. ﺍﺯ ﺍﻳﻦ ﺭﻭ ﻣﺪﺍﺭﻫﺎﻱ ﻣﻨﻄﻘﻲ ﺗﺮﺗﻴﺒﻲ ﺩﺍﺭﺍﻱ ﺣﺎﻓﻈﻪ ﻣﻲﺑﺎﺷﻨﺪ.‬ ‫ﻣﺎﻧﻨﺪ ﻣﺪﺍﺭﻫﺎﻱ ﺩﻳﺠﻴﺘﺎﻟﻲ ﺷﻤﺎﺭﺷﮕﺮ ﻭ ﻣﺤﺎﺳﺒﺎﺗﻲ )ﻣﺎﻧﻨﺪ ﻣﻴﻜﺮﻭﭘﺮﻭﺳﺴﻮﺭﻫﺎ ﻭ ﻏﻴﺮﻩ. . . (‬ ‫۴‐۲‐ ﻣﺸﺨﺼﻪﻫﺎﻱ ﻋﻤﻮﻣﻲ‪ IC‬ﻫﺎﻱ ﺩﻳﺠﻴﺘﺎﻝ‬ ‫ﺍﻟﻒ ‐ ﺗﻜﻨﻮﻟﻮﮊﻱﻫﺎﻱ ﻣﺨﺘﻠﻔﻲ ﺩﺭ ﺳﺎﺧﺖ ﺍﻧﻮﺍﻉ ﻣﺨﺘﻠﻒ ‪ IC‬ﻫﺎﻱ ﺩﻳﺠﻴﺘﺎﻝ )ﻣﺎﻧﻨﺪ ‪Logic gates‬‬ ‫)‪ (….Shift registers, Counters, Flipflops‬ﺑﻜﺎﺭ ﮔﺮﻓﺘﻪ ﻣﻲﺷﻮﺩ. ﺍﺯ ﺗﻜﻨﻮﻟﻮﮊﻱﻫﺎﻱ ﻣﺮﺳﻮﻡ ﻛﻪ‬ ‫ﺩﺍﺭﺍﻱ ﺑﻴﺸﺘﺮﻳﻦ ﻛﺎﺭﺑﺮﺩ ﻫﺴﺘﻨﺪ ﻣﻲﺗﻮﺍﻥ ‪CMOS ، (Transisror - Transisror Logic) TTL‬‬ ‫)‪(Complementary metal oxide Semiconductors‬ﻭ ‪ (Emitter Coupled Logic) ECL‬ﺭﺍ ﻧﺎﻡ‬ ‫ﺑﺮﺩ. ﻫــﺮ ﻳﻚ ﺍﺯ ﺍﻳﻦ ﺗﻜﻨﻮﻟﻮﮊﻱﻫﺎ ﺩﺍﺭﺍﻱ ﻣﺰﺍﻳﺎ ﻭ ﻣﻌﺎﻳﺒﻲ ﻫﺴﺘﻨﺪ. ﺍﺯ ﺟﻤﻠﻪ ﻣﻌﻴﺎﺭﻫﺎﻱ ﻣﻘﺎﻳﺴﻪ ﻭ ﻣﺸﺨﺼﻪﻫﺎﻱ‬ ‫‪IC‬ﻫﺎﻱ ﺩﻳﺠﻴﺘﺎﻟﻲ ﻣﻲﺗﻮﺍﻥ ﺑﻪ ﺳﺮﻋﺖ، ‪ Fan in / Fan out‬ﻭ ﺣﺴﺎﺳﻴﺖ ﻧﻮﻳﺰ ﺭﺍ ﻧﺎﻡ ﺑﺮﺩ.‬ ‫• ﺗﺄﺧﻴﺮ ﺍﻧﺘﻘﺎﻝ، ‪(propagation delay) tpd‬‬ ‫‪Input‬‬ ‫‪ tpd‬ﻋﺒﺎﺭﺗﺴﺖ ﺍﺯ ﺗﺄﺧﻴﺮ ﺑﻴﻦ ﺗﻐﻴﻴﺮ ﺩﺭ ﻭﺭﻭﺩﻱ ﻭ ﺗﻐﻴﻴـﺮ‬ ‫ـ‬ ‫ـ‬ ‫ـ‬ ‫ـ‬ ‫ﺣﺎﺻـﻠﻪ ﺩﺭ ﺧ ــﺮﻭﺟﻲ. ﺑ ـﺮﺍﻱ ﻣﺤﺎﺳـﺒﻪ‪ ، tpd‬ﺯﻣ ـﺎﻥ‬ ‫ـ‬ ‫ﻋﺒــــﻮﺭ ﻭﻟﺘـــﺎﮊﻫﺎﻱ ﻭﺭﻭﺩﻱ ﻭ ﺧﺮﻭﺟــﻲ ﺍﺯ ﻣﻘـــﺎﺩﻳﺮ‬ ‫ﻣﻴــﺎﻧﻲ )‪ (midpoint‬ﻣﻮﺭﺩ ﺍﺳﺘﻔﺎﺩﻩ ﻗﺮﺍﺭ ﻣﻲﮔﻴﺮﺩ.‬ ‫‪Output‬‬ ‫‪tpd‬‬ ‫‪tpd‬‬ ‫• ﺯﻣﺎﻥﻫﺎﻱ ﺧﻴﺰ ﻭ ﺍﻓﺖ ﺧﺮﻭﺟﻲ)‪(output rise and fall time‬‬ ‫ﺯﻣﺎﻥ ﺧﻴﺰ ‪ (Rise time) tr‬ﻋﺒﺎﺭﺗﺴﺖ ﺍﺯ ﺯﻣﺎﻥ ﻻﺯﻡ ﺑﺮﺍﻱ ﺗﻐﻴﻴﺮ‬ ‫%09‬ ‫ﺧﺮﻭﺟﻲ ﺍﺯ ‪ 0.1VHigh‬ﺑﻪ ‪0.9VHigh‬‬ ‫‪Output‬‬ ‫%01‬ ‫ﺯﻣﺎﻥ ﺍﻓﺖ ‪ (Fall time) tF‬ﻋﺒﺎﺭﺗﺴﺖ ﺍﺯ ﺯﻣﺎﻥ ﻻﺯﻡ ﺑﺮﺍﻱ ﺗﻐﻴﻴﺮ‬ ‫ﺧﺮﻭﺟﻲ ﺍﺯ ‪ 0.9VHigh‬ﺑﻪ ‪0.1VHigh‬‬ ‫• ‪ Fan in‬ﻭ ‪Fan out‬‬ ‫‪tf‬‬ ‫‪Fall Time‬‬ ‫‪tr‬‬ ‫‪Rise time‬‬ ‫ﻭﺭﻭﺩﻱ ﻳﻚ ‪ gate‬ﺳﺎﺩﻩ )ﻣﺎﻧﻨﺪ ‪ (Not‬ﺑﻌﻨﻮﺍﻥ “ﺑﺎﺭ ﺍﺳﺘﺎﻧﺪﺍﺭﺩ-‪” Standard Load‬ﻧﺎﻣﻴﺪﻩ ﻣﻲﺷﻮﺩ. ﺗﻮﺍﻧــﺎﻳﻲ ﺧﺮﻭﺟﻲ‬ ‫ﻳﻚ ‪ gate‬ﺑﺮﺍﻱ ﺗﺤﺮﻳﻚ ﻭﺭﻭﺩﻱ ﺳﺎﻳﺮ‪ gate‬ﻫﺎ ﺑﻌﻨﻮﺍﻥ ‪ Fan out‬ﺑــﺮﺍﻱ ‪ gate‬ﻣﺰﺑﻮﺭ ﺷﻨﺎﺧﺘﻪ ﻣﻲﺷـﻮﺩ. ﻭﻗﺘـﻲ ﮔﻔﺘـﻪ‬ ‫ﻣﻲﺷﻮﺩ ﻛﻪ ﻳﻚ ‪ gate‬ﺧﺎﺹ ﺩﺍﺭﺍﻱ ‪ Fan out‬ﺑﺮﺍﺑﺮ٠١ﻣﻲﺑﺎﺷﺪ ﺍﻳﻦ ﺑﺪﻳﻦ ﻣﻌﻨﺎﺳﺖ ﻛﻪ ﺧﺮﻭﺟﻲ ‪ gate‬ﻣﺰﺑﻮﺭ ﻣﻲﺗﻮﺍﻧﺪ‬ ‫٠١ ﮔﻴﺖ ﺳﺎﺩﻩ )ﺑﺎﺭ ﺍﺳﺘــﺎﻧﺪﺍﺭﺩ( ﺭﺍ ﺗﺤﺮﻳﻚ ﻧﻤﺎﻳﺪ.‬ ‫ﻭﺭﻭﺩﻱ ﺑﻌﻀﻲ ﺍﺯ‪ gate‬ﻫﺎ ﺍﺯ ﺩﻳﺪﮔﺎﻩ ﻣﺪﺍﺭ ﺗﺤﺮﻳﻚ ﻛﻨﻨﺪﻩ، ﻣﻌﺎﺩﻝ ﭼﻨﺪﻳﻦ ﺑﺮﺍﺑﺮ ﻳﻚ “ﺑﺎﺭ ﺍﺳﺘﺎﻧﺪﺍﺭﺩ” ﻣﻴﺒﺎﺷﺪ. ﻭﻗﺘﻲ‬ ‫ﮔﻔﺘﻪ ﻣﻲﺷﻮﺩ ﻛﻪ ﻳﻚ ‪ gate‬ﺧﺎﺹ ﺩﺍﺭﺍﻱ ‪ Fan in‬ﺑﺮﺍﺑﺮ٣ ﻣﻲﺑﺎﺷﺪ، ﺍﻳﻦ ﺑﺪﻳﻦ ﻣﻌﻨﺎﺳﺖ ﻛﻪ ﻭﺭﻭﺩﻱ ‪ gate‬ﻣﺰﺑﻮﺭ ﺍﺯ‬ ‫ﻧﻈﺮ ﺧﺮﻭﺟﻲ ‪ gate‬ﺗﺤﺮﻳﻚ ﻛﻨﻨﺪﻩ، ﻣﻌﺎﺩﻝ ٣ ﺑﺮﺍﺑﺮ ﻳﻚ “ﺑﺎﺭ ﺍﺳﺘﺎﻧﺪﺍﺭﺩ” ﻣﻲﺑﺎﺷﺪ.‬ ‫• ﺣﺴﺎﺳﻴﺖ ﺑﻪ ﻧﻮﻳﺰ ‪noise immunity‬ﻳﺎ)‪(noise margin‬‬ ‫ﻋﺒﺎﺭﺗﺴﺖ ﺍﺯ ﺣﺪﺍﻛﺜﺮ ﺩﺍﻣﻨﻪ ﭘﺎﻟﺴﻲ ﻛﻪ ﺩﺭ ﺻﻮﺭﺕ ﺍﻋﻤﺎﻝ ﺑﻪ ﻭﺭﻭﺩﻱ ﻳﻚ ‪ ، gate‬ﺑﻪ ﺧﺮﻭﺟﻲ ﺁﻥ ﺍﻧﺘﻘﺎﻝ ﻧﻴﺎﺑﺪ. ﺑﺮﺍﻱ‬ ‫ﻣﺜﺎﻝ ﻫﻤﺎﻧﻄﻮﺭ ﻛﻪ ﺍﺷﺎﺭﻩ ﺷﺪ‪ TTL‬ﻫﺎ ﺩﺍﺭﺍﻱ ﺣﺪﺍﻗﻞ ‪ noise immunity‬ﺑﺮﺍﺑﺮ ﺑﺎ ‪ 0.4V‬ﻣﻲﺑﺎﺷﻨﺪ.‬ ‫ﺏ‐ ﺳﻄﻮﺡ ﻭﻟﺘﺎﮊ ‪ High‬ﻭ ‪ Low‬ﺑﺮﺍﻱ ‪ TTL، CMOS‬ﻭ‪ ECL‬ﻫﺎ‬ ‫ﺩﺭ ﻳﻚ ‪ TTL‬ﻭﺭﻭﺩﻱ ﺯﻳﺮ ‪0.8V‬ﺑﻌﻨﻮﺍﻥ‬ ‫ﺻﻔﺮ ﻣﻨﻄﻘﻲ ﺗﻌﺒﻴﺮ ﻣﻲﺷﻮﺩ‬ ‫‪Noise‬‬ ‫‪Margin‬‬ ‫ﻭﻟﺘﺎﮊ ﺧﺮﻭﺟﻲ ﻳﻚ ‪ TTL‬ﺑﺮﺍﻱ ﺻﻔﺮ‬ ‫ﻣﻨﻄﻘﻲ ﺯﻳﺮ ‪ 0.4 V‬ﻣﻲﺑﺎﺷﺪ.‬ ‫‪ ‐ Input‬ﻣﺼﺮﻑ ﻛﻨﻨﺪﻩ‬ ‫‪Logic‬‬ ‫‪One‬‬ ‫‪undefined‬‬ ‫‪ ‐ Output‬ﺗﻮﻟﻴﺪ ﻛﻨﻨﺪﻩ‬ ‫‪Logic‬‬ ‫‪Zero‬‬ ‫‪Logic‬‬ ‫‪One‬‬ ‫‪undefined‬‬ ‫‪Logic‬‬ ‫‪Zero‬‬ ‫‪0.4V‬‬ ‫‪>2V‬‬ ‫‪0.8 2 V‬‬ ‫‪<0.8V‬‬ ‫‪>2.4V‬‬ ‫‪0.4 2.4 V‬‬ ‫‪< 0. 4V‬‬ ‫‪TTL‬‬ ‫‪>1V‬‬ ‫‪>3.5V‬‬ ‫‪1.5 3.5V‬‬ ‫‪<1.5V‬‬ ‫‪>4.6V‬‬ ‫‪0.4 4.6V‬‬ ‫‪< 0. 4V‬‬ ‫‪CMOS 5V‬‬ ‫‪>4V‬‬ ‫‪>9.5V‬‬ ‫‪4.8 9.5V‬‬ ‫‪<4.8V‬‬ ‫‪>14.4V‬‬ ‫‪0.5 14.5V‬‬ ‫‪< 0. 6V‬‬ ‫‪CMOS 15V‬‬ ‫‪>‐0.9V‬‬ ‫‪‐0.9 ‐1.7V‬‬ ‫‪<‐1.7V‬‬ ‫ﻣﺸﺨﺼﻪﻫﺎﻱ ﻋﻤﻮﻣﻲ ﺍﻧﻮﺍﻉ ‪ TTL، CMOS‬ﻭ ‪ ECL‬ﺩﺭ ﺟﺪﻭﻝ ﺻﻔﺤﻪ ﺑﻌﺪ ﺁﻣﺪﻩ ﺍﺳﺖ‬ ‫‪ECL‬‬ ‫ﺝ – ﺭﻓﺘﺎﺭ ﻭﺭﻭﺩﻱ ﻭ ﺧﺮﻭﺟﻲ ‪ TTL‬ﻭ‪ CMOS‬ﻫﺎ‬ ‫• ﺑﻄﻮﺭ ﻋﻤﻮﻣﻲ ﺧﺮﻭﺟﻲ ﻳﻚ ‪ gate‬ﻣﻲﺗﻮﺍﻧﺪ ﺟﻬﺖ ﺗﺤﺮﻳﻚ 01 ﮔﻴﺖ ﺩﻳﮕﺮ )ﻳﺎ ﺑﻴﺸﺘﺮ( ﺍﺯ ﻫﻤﺎﻥ ﺧﺎﻧﻮﺍﺩﻩ‬ ‫ﺑﻜﺎﺭﮔﺮﻓﺘﻪ ﺷﻮﺩ. ﺑﺮﺍﻱ ﻣﺜﺎﻝ ﺧﺮﻭﺟﻲ ﻳﻚ ‪ TTL-LS‬ﻣﻲﺗــﻮﺍﻧﺪ ﻭﺭﻭﺩﻱ 01 ﮔﻴﺖ ﺍﺯ ﻧـﻮﻉ ‪ TTL-LS‬ﺭﺍ ﺗﺤﺮﻳﻚ‬ ‫)‪(drive‬ﻧﻤﺎﻳﺪ.‬ ‫• ﺩﺭ ﺻﻮﺭﺕ ﻧﻴﺎﺯ ﺑﻪ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﺍﻧﻮﺍﻉ ﻣﺨﺘﻠﻒ‪ IC‬ﻫﺎﻱ ﺩﻳﺠﻴﺘﺎﻝ ﺍﺯ ﺧﺎﻧﻮﺍﺩﻩﻫﺎﻱ ﻣﺨﺘﻠﻒ )ﻣﺜﻼ ‪ TTL-LS‬ﺑﺎ-‪TTL‬‬ ‫ﹰ‬ ‫‪N‬ﻳﺎ ‪ TTL‬ﺑﺎ ‪ CMOS‬ﻳﺎ . . . . (، ﺑــﺎ ﺗﻮﺟﻪ ﺑﻪ ﺗﻔــﺎﻭﺕ ﺩﺭ ﺟﺮﻳﺎﻥﻫﺎﻱ ﻭﺭﻭﺩﻱ ﻣﻮﺭﺩ ﻧﻴﺎﺯ، ﺟﺮﻳﺎﻥ ﺧﺮﻭﺟﻲ ﻗﺎﺑﻞ‬ ‫ﺗﺄﻣﻴﻦ، ﺳﻄــﻮﺡ ﻭﻟﺘﺎﮊ ‪ High‬ﻭ ‪ ، Low‬ﺑﺎﻳﺪ ﺗﻤﻬﻴﺪﺍﺕ ﻻﺯﻡ ﺑﻜﺎﺭﮔﺮﻓﺘﻪ ﺷﻮﺩ.‬ ‫• ﺑﺎ ﺗﻮﺟﻪ ﺑﻪ ﺗﺸﺎﺑﻪ ﻛﺎﻣﻞ ﺳﻄﻮﺡ ﻭﻟﺘﺎﮊ ‪ High‬ﻭ ‪ Low‬ﺩﺭ ﻛﻠﻴﻪ ﺧﺎﻧﻮﺍﺩﻩﻫﺎﻱ ‪ ، TTL‬ﺍﺗﺼﺎﻝ ﺁﻧﻬــﺎ ﺑﺎﻳﺪ ﺑﺎ ﺗﻮﺟﻪ‬ ‫ﺑﻪ ﻣﺤﺪﻭﺩﻳﺖﻫﺎﻱ ﺟﺮﻳﺎﻥ ﻗﺎﺑﻞ ﺗﺄﻣﻴﻦ ﺧﺮﻭﺟﻲ ﻭ ﺟﺮﻳﺎﻥﻫﺎﻱ ﻣﻮﺭﺩ ﻧﻴــﺎﺯ ﻭﺭﻭﺩﻱ ﺻﻮﺭﺕ ﮔﻴﺮﺩ، ﻗﻮﺍﻋﺪ ﻛﻠﻲ ﺍﺗﺼﺎﻝ‬ ‫‪TTL‬ﻫﺎ ﭼﻨﻴﻦ ﺍﺳﺖ‬ TTL Cookbook :‫ﻣﺮﺟﻊ‬ ‫ )ﻭ ﺑـﺎ ﺗﻮﺟـﻪ ﺑـﻪ ﺗﺸـﺎﺑﻪ‬CMOS ‫ ﻭ‬TTL ‫ ﺍﺯ ﻧـﻮﻉ‬NAND gate ‫• ﺑﺎ ﺗﻮﺟـﻪ ﺑـﻪ ﺳـﺎﺧﺘﻤﺎﻥ ﺩﺍﺧﻠـﻲ ﻳـﻚ‬ ‫ ﻫـﺎﻱ ﺩﻳﺠﻴﺘـــﺎﻟﻲ( ﻣـﻲﺗــﻮﺍﻥ ﺑـﻪ‬IC‫ ﻫـﺎ ﻭ‬gate‫ ﺑـﺎ ﺳـﺎﻳﺮ‬NAND gate ‫ﺑﺨﺶﻫﺎﻱ ﻭﺭﻭﺩﻱ ﻭ ﺧﺮﻭﺟـﻲ‬ .‫ ﻫﺎ ﺩﺳﺖ ﻳﺎﻓﺖ‬CMOS‫ ﻫﺎ ﻭ‬TTL‫ﻧﺘﻴﺠﻪﮔﻴﺮﻱﻫﺎﻳﻲ ﺑﺸﺮﺡ ﺯﻳﺮ ﺩﺭ ﻣﻮﺭﺩ ﺭﻓﺘﺎﺭ ﻭﺭﻭﺩﻱ ﻭ ﺧﺮﻭﺟﻲ‬ VCC 1.6K H 4K A B Q1 L D2 D1 +5V L Q2 L VDD 130Ω PMOS Q1 Q3 H + VDD Q4 A.B=A+B A 1.0K On B On Hx Q4 L Off CMOS AND V B 2 = O ⇒ V E 2 = O ⇒ Q 4 Off & Q3 On A or B Low ⇒ x = High A 0 0 1 1 B 0 1 0 1 Y=AB Z=AB 0 1 0 1 0 1 1 0 Q NMOS Off A or B Low ⇒ Q 1 On ⇒ VCE 1 ~ O ⇒ Q5 Q3 L + VDD TTL NAND H Q2 ON when X Low Q=A.B Q6 ON when X High ‫• ﻭﺭﻭﺩﻱ ‪ TTL‬ﺩﺭ ﻭﻟﺘﺎﮊﻫﺎﻱ ‪ VLow‬ﻣﻮﻟﺪ ﺟﺮﻳﺎﻥ ﺑﻮﺩﻩ ﻭ ﺩﺭ ﻭﻟﺘﺎﮊﻫﺎﻱ ‪ VHigh‬ﺟﺮﻳﺎﻥ ﻧﺴﺒﺘﺎ ﭘﺎﻳﻴﻦ )ﻛﻤﺘﺮ ﺍﺯ‬ ‫ﹰ‬ ‫‪ (40 µA‬ﻣﺼﺮﻑ ﻣﻲﻧﻤﺎﻳﺪ )ﻛﻪ ﺟﺮﻳﺎﻥ ﺗﻐﺬﻳﻪ ﻣﻌﻜﻮﺱ 1‪ D‬ﻭ 2‪ D‬ﻫﺴﺘﻨﺪ(‬ ‫• ﺩﺭ ‪ TTL & CMOS‬ﻫﺎ ﺑﺎ ﺗﻮﺟﻪ ﺑﻪ ﻭﺟﻮﺩ ﺩﻳﻮﺩﻫﺎﻱ ﻣﺤﺎﻓﻆ ﺩﺭ ﻭﺭﻭﺩﻱ، ﻛﺎﻫﺶ ﻭﻟﺘﺎﮊ ﻭﺭﻭﺩﻱ ﻛﻤﺘــﺮ ﺍﺯ -‬ ‫‪0.7V‬ﻣﻮﺟﺐ ﻫﺪﺍﻳﺖ ﺩﻳﻮﺩﻫﺎ ﻣﻲﮔﺮﺩﺩ .ﺩﻳﻮﺩﻫﺎﻱ ﻣﺤﺎﻓﻆ ﺑﺮﺍﻱ‪ CMOS‬ﻫﺎ ﻧﻘﺶ ﻣﺤﺎﻓﻈﺖ ﺭﺍ ﺩﺭ ﺑﺮﺍﺑﺮ‬ ‫ﺍﻟﻜﺘﺮﻳﺴﻴﺘﻪ ﺳﺎﻛﻦ ﺭﺍ ﻧﻴﺰ ﻋﻬﺪﻩﺩﺍﺭ ﻫﺴﺘﻨﺪ .‬ ‫ﺑﺎ ﺗﻮﺟﻪ ﺑﻪ ﻭﺟﻮﺩ ‪ MOSFET‬ﺩﺭ ﻭﺭﻭﺩﻱ‪ CMOS‬ﻫﺎ ، ﺟﺮﻳﺎﻥ ﻭﺭﻭﺩﻱ ﻣﺼﺮﻓﻲ ﺩﺭ ﻓﺮﻛﺎﻧﺲﻫـﺎﻱ ﭘﺎﻳﻴﻦ ﻗﺎﺑﻞ‬‫ﺻﺮﻓﻨﻈﺮ ﺍﺳﺖ )ﻛﻤﺘﺮ ﺍﺯ ‪ (10-5µA‬ﻭ ﺑﺎ ﺍﻓﺰﺍﻳﺶ ﻓﺮﻛﺎﻧﺲ ﺑﻌﻠﺖ ﻇﺮﻓﻴﺖ ﺧﺎﺯﻧﻲ ﺑﻴﻦ ﮔﻴﺖ ﻭ ﻛــﺎﻧــﺎﻝ ﺍﻓﺰﺍﻳﺶ‬ ‫ﻣﻲﻳﺎﺑﺪ.‬ ‫‪TTL emitter breakdown‬‬ ‫)‪(except 74LSxx‬ ‫‪CMOS‬‬ ‫‪diode‬‬ ‫‪74LSxx diode‬‬ ‫)‪(15V breakdown‬‬ ‫‪Input Voltage‬‬ ‫)‪TTL (Hi‬‬ ‫)‪1µA (typ‬‬ ‫‪40 µA max‬‬ ‫‪CMOS‬‬ ‫‪<<1µA‬‬ ‫‪leakage‬‬ ‫‪Input‬‬ ‫‪Current‬‬ ‫‪+5V‬‬ ‫) ‪⎧ 74 xx : − 1 . 0 mA ( typ‬‬ ‫⎪‬ ‫) ‪⎨ 74 LSxx : − 0 . 22 mA ( typ‬‬ ‫) ‪⎪ 74 Sxx : − 1 . 4 mA ( typ‬‬ ‫⎩‬ ‫) ‪TTL ( Low‬‬ ‫‪diode‬‬ ‫• ﻣﺮﺣﻠﻪ ﺧﺮﻭﺟﻲ ‪ TTL‬ﻣﺘﺸﻜﻞ ﺍﺯ ﺩﻭ ‪ npn‬ﺑﺸﻜﻞ ‪ push-pull‬ﺍﺳﺖ ﻛﻪ ﻫﻤﻮﺍﺭﻩ ﻳﻜﻲ ﺭﻭﺷﻦ ﻭ ﺩﻳﮕـﺮﻱ‬ ‫ﺧﺎﻣﻮﺵ ﺍﺳﺖ . 3‪ Q‬ﻭﻗﺘﻲ ﺭﻭﺷﻦ ﺑﺎﺷﺪ ﻣﻲﺗﻮﺍﻧﺪ ﺟﺮﻳﺎﻥ ﺑﺎﻻﻳﻲ ﺭﺍ ﺗﺄﻣﻴﻦ ﻧﻤﺎﻳﺪ . 4‪ Q‬ﻭﻗﺘﻲ ﺭﻭﺷـﻦ ﺑﺎﺷـﺪ‬ ‫ﻣﻲﺗﻮﺍﻧﺪ ﺟﺮﻳﺎﻥ ﺑﺎﻻﻳﻲ ﺭﺍ ﺑﻪ ﺯﻣﻴﻦ ﻫﺪﺍﻳﺖ ﻛﻨﺪ )ﺑﺮﺍﻱ ‪ TTL-N‬ﺍﻳﻦ ﺟﺮﻳﺎﻥ ﺣﺪﻭﺩﹰﺍ ‪16 mA‬ﻣﻲﺑﺎﺷﺪ(‬ ‫• ﻣﺮﺣﻠﻪ ﺧﺮﻭﺟﻲ ‪ CMOS‬ﻣﺘﺸﻜـﻞ ﺍﺯ ﺩﻭ ‪ MOSFET‬ﺑﺸﻜﻞ ﻣﻜﻤﻞ ﻫﻢ ﻣﻲﺑﺎﺷﺪ. ﻫﻤـﻮﺍﺭﻩ ﻳﻜﻲ ﺭﻭﺷـﻦ ﻭ‬ ‫ﺩﻳﮕــﺮﻱ ﺧﺎﻣـــﻮﺵ ﺍﺳﺖ. ﻫﺮ ﻳﻚ ﺍﺯ ﺩﻭ ﺗﺮﺍﻧﺰﻳﺴﺘـﻮﺭ 5‪ Q‬ﻭ 6‪ Q‬ﺩﺭﺻـﻮﺭﺕ ﺭﻭﺷﻦ ﺑﻮﺩﻥ ﻣﺎﻧﻨﺪ ﻳﻚ ﻣﻘﺎﻭﻣﺖ‬ ‫ﭼﻨﺪ ﺻﺪ ﺍﻫﻤﻲ ﻋﻤﻞ ﻣﻲﻧﻤﺎﻳﺪ. ﻟﺬﺍ ﺍﻓﺰﺍﻳﺶ ﺟﺮﻳﺎﻥ ﺧﺮﻭﺟـﻲ ﻣﻮﺟـﺐ ﻓﺎﺻـﻠﻪ ﮔـﺮﻓﺘﻦ ﻭﻟﺘـﺎﮊ ﺍﺯ ‪ ground‬ﻳـﺎ‬ ‫ﻭﻟﺘﺎﮊ ﻣﻨﺒﻊ ﺗﻐﺬﻳﻪ ﻣﻲﮔﺮﺩﺩ.‬ ‫ﺑﺮﺍﻱ ﺍﻃﻼﻋﺎﺕ ﺑﻴﺸﺘﺮ ﺩﺭ ﻣﻮﺭﺩ ﻧﺤﻮﻩ ﺍﺗﺼﺎﻝ‪ TTL‬ﻫﺎ ﻭ‪ CMOS‬ﻫﺎ ﺑﻪ ﺑﺨﺶ30.9 ﺻﻔﺤﻪ٤٨٣ ﺍﺯ ﻛﺘﺎﺏ ‪Art‬‬ ‫‪of Electronics‬ﻣﺮﺍﺟﻌﻪ ﺷﻮﺩ.‬ (Boolean Algebra)‫3-4ﺟﺒﺮ ﺑﻮﻝ‬(Basic Logic gates)‫1-3-4ﮔﻴﺖﻫﺎﻱ ﺳﺎﺩﻩ‬Contact A Contact B • AND gate Coil Y Coil Y is energized (True) if Contacts A AND B are energized (True) Ladder digration A Y B Output Y is energized (True) if both inputs A AND B are High (True) AND gate symbol ‫ﻧﻤﺎﺩ‬ (7408,4081) Y=A.B Logical AND Operator A 0 0 1 1 B 0 1 0 1 Y=AB 0 0 0 1 Truth Table ‫ﺟﺪﻭﻝ ﺭﺍﺳﺘﻲ‬ • OR gate Coil Y Contact A Coil Y is energized (True) if eiher Contacts A OR B are energized (True) Contact B Ladder diagram A B Y Output Y is high (True) if either inputs A OR B are High (True) OR gate Symbol ‫ﻧﻤﺎﺩ‬ (7432,4071) Y=A+B Logical OR Operator A 0 0 1 1 B 0 1 0 1 Y=A+B 0 1 1 1 Truth Table ‫ﺟﺪﻭﻝ ﺭﺍﺳﺘﻲ‬ • INVERTER / NOT gate NC Contact A Coil Y Coil Y is energized (True) if Contact A is NOT energized (False) Ladder diagram A Y Output Y is high (True) if input A is Low (False) NOT gate Symbol (7404,4069) Y=A A 0 1 Y 1 0 Truth Table ‫ﺟﺪﻭﻝ ﺭﺍﺳﺘﻲ‬ (Gate Combinations)‫2-3-4ﮔﻴﺖﻫﺎﻱ ﺗﺮﻛﻴﺒﻲ‬A B • NAND gate Y Coil Z is energized (True) if Contacts A AND B are NOT both energized (True) Y Z Ladder diagram A Y B NAND gate symbol (7400,4011) Z=A.B Output Z is High (True) if inputs A OR B are NOT both High (True) A 0 0 1 1 B 0 1 0 1 Y=AB Z=AB 0 1 0 1 0 1 1 0 Truth Table ‫ﺟﺪﻭﻝ ﺭﺍﺳﺘﻲ‬ A • NOR gate Y Coil Z is energized (True) if Contacts A OR B are NOT either energized (True) B Y Z A Output Z is High (True) if inputs A OR B are NOT either High (True) Y B (7402,4001) Z=A+B A 0 0 1 1 B 0 1 0 1 Y=A+B Z=A+B 0 1 1 0 1 0 1 0 Truth Table ‫ﺟﺪﻭﻝ ﺭﺍﺳﺘﻲ‬ A • XOR gate Y B A Y B X Coil Z is energized (True) if EITHER Contacts A X OR Contact B are energized (& not both) Z A B Z Z=A+B Output Z is High (True) if only one of the two inpots are High (True) A 0 0 1 1 B 0 1 0 1 Z=A + B 0 1 1 0 Truth Table ‫ﺟﺪﻭﻝ ﺭﺍﺳﺘﻲ‬ ‫2-3-4- ﻗﻮﺍﻧﻴﻦ ﺟﺒﺮ ﺑﻮﻟﻲ‬ ‫• ﻛﻠﻴﻪ ﻗﻮﺍﻧﻴﻦ ﺟﺒﺮ ﺑﻮﻟﻲ ﺑﺎ ﺗﺸﻜﻴﻞ ﺟﺪﻭﻝ ﺭﺍﺳﺘﻲ ‪ Truthtable‬ﻗﺎﺑﻞ ﺍﺛﺒﺎﺕ ﺍﺳﺖ. ﻟﻴﺴﺖ ﻗﻮﺍﻧﻴﻦ ﺑﺸﺮﺡ‬ ‫ﺯﻳﺮ ﻣﻲﺑﺎﺷﺪ.‬ ‫1.‪A‬‬ ‫0‬ ‫1‬ ‫1+‪A‬‬ ‫1‬ ‫1‬ ‫‪A‬‬ ‫0‬ ‫1‬ ‫‪A.A‬‬ ‫0‬ ‫1‬ ‫‪A+A‬‬ ‫0‬ ‫1‬ ‫‪A‬‬ ‫0‬ ‫1‬ ‫1 = 1 + ‪(3) A‬‬ ‫‪(4) A . 1 = A‬‬ ‫:‪Null / Identity rules‬‬ ‫‪(1) A + 0 = A‬‬ ‫0 = 0 . ‪(2) A‬‬ ‫‪(7) A + A = A‬‬ ‫‪(8) A . A = A‬‬ ‫1 = ‪(5) A + Ā‬‬ ‫0 = ‪(6) A . Ā‬‬ ‫‪(10) A + B = B + A‬‬ ‫)‪(12) (A + B) + C = A + (B + C‬‬ ‫:)ﺍﺻﻞ ﺟﺎﺑﺠﺎﻳﻲ( ‪Commutative Low‬‬ ‫‪(9) A . B = B . A‬‬ ‫:)ﻗﺎﻧﻮﻥ ﺷﺮﻛﺖﭘﺬﻳﺮﻱ( ‪Associative Law‬‬ ‫)‪(11) (A . B) . C = A . (B . C‬‬ ‫:)ﻗﻀﻴﻪ ﺩﻣﻮﺭﮔﺎﻥ( ‪DeMorgan`s Theorem‬‬ ‫‪(13) = A . B = A + B‬‬ ‫‪(14) A + B = A .B‬‬ ‫ﺑﺮﻃﺒﻖ ﻗﻀﻴﻪ ﺩﻣﻮﺭﮔﺎﻥ ﺑﺮﺍﻱ ﺗﺸﻜﻴﻞ ﻣﻜﻤﻞ )‪ (complement‬ﺑﺮﺍﻱ ﻳﻚ ﻋﺒﺎﺭﺕ‬ ‫1- ﻛﻠﻴﻪ ﻋﻤﻠﮕﺮﻫﺎﻱ ”+“ )‪ (operators‬ﺭﺍ ﺑﺎ “.” ﺟﺎﻳﮕﺰﻳﻦ ﻣﻲﻧﻤﺎﻳﻴﻢ.‬ ‫2- ﻛﻠﻴﻪ ﻋﻤﻠﮕﺮﻫﺎﻱ ”.“ )‪ (operators‬ﺭﺍ ﺑﺎ “+” ﺟﺎﻳﮕﺰﻳﻦ ﻣﻲﻧﻤﺎﻳﻴﻢ.‬ ‫3- ﺑﺠﺎﻱ ﻫﺮ ﻳﻚ ﺍﺯ ﺟﻤﻼﺕ ﺍﺯ ﻋﺒﺎﺭﺕ ﺍﻭﻟﻴﻪ، ﻣﻜﻤﻞ ﺁﻥ ﺭﺍ ﺟﺎﻳﮕﺰﻳﻦ ﻣﻲﻧﻤﺎﻳﻴﻢ.‬ ‫ﺑﺮﺍﻱ ﻣﺜﺎﻝ:‬ ‫) ‪( A + ( B . C )) = A . ( B . C ) = A . ( B + C‬‬ ‫ﺍﺛﺒﺎﺕ ﺗﻮﺳﻂ ﺗﺸﻜﻴﻞ ﺟﺪﻭﻝ ﺭﺍﺳﺘﻲ )ﺑﺮﺍﻱ ﻗﻀﻴﻪ ﺩﻣﻮﺭﮔﺎﻥ(‬ ‫‪A. B = A + B‬‬ ‫‪A+B‬‬ ‫1‬ ‫1‬ ‫1‬ ‫0‬ ‫‪A.B‬‬ ‫1‬ ‫1‬ ‫1‬ ‫0‬ ‫‪A.B‬‬ ‫0‬ ‫0‬ ‫0‬ ‫1‬ ‫‪B‬‬ ‫1‬ ‫0‬ ‫1‬ ‫0‬ ‫‪A + B = A. B‬‬ ‫‪A‬‬ ‫1‬ ‫1‬ ‫0‬ ‫0‬ ‫‪B‬‬ ‫0‬ ‫1‬ ‫0‬ ‫1‬ ‫‪A‬‬ ‫0‬ ‫0‬ ‫1‬ ‫1‬ ‫‪A+B‬‬ ‫1‬ ‫0‬ ‫0‬ ‫0‬ ‫‪B A+B A.B‬‬ ‫1‬ ‫0‬ ‫1‬ ‫0‬ ‫1‬ ‫0‬ ‫1‬ ‫1‬ ‫0‬ ‫0‬ ‫1‬ ‫0‬ ‫‪A‬‬ ‫1‬ ‫1‬ ‫0‬ ‫0‬ ‫‪B‬‬ ‫0‬ ‫1‬ ‫0‬ ‫1‬ ‫‪A‬‬ ‫0‬ ‫0‬ ‫1‬ ‫1‬ ‫)ﻗﺎﻧﻮﻥ ﭘﺨﺶﭘﺬﻳﺮﻱ ﻳﺎ ﺗﻮﺯﻳﻌﻲ( ‪Distributive Low‬‬ ‫‪(15) A . (B + C) = A . B + A . C‬‬ ‫)‪(16) A + B . C = (A + B) . (A + C‬‬ ‫‪(17 ) A + A B = A + B‬‬ ‫ﻣﺠﺪﺩﹰﺍ ﺍﻳﻦ ﻗﻮﺍﻧﻴﻦ ﻧﻴﺰ ﺗﻮﺳﻂ ﺗﺸﻜﻴﻞ ﺟﺪﻭﻝ ﺭﺍﺳﺘﻲ ﻗﺎﺑﻞ ﺍﺛﺒﺎﺕ ﻣﻲﺑﺎﺷﻨﺪ. ﻗﺎﻧﻮﻥ )٦١( ﻭ )۷۱( ﺑﺎ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﻗﻀﻴﻪ‬ ‫ﺩﻣﻮﺭﮔﺎﻥ ﻧﻴﺰ ﻗﺎﺑﻞ ﺍﺛﺒﺎﺕ ﻣﻲﺑﺎﺷﻨﺪ.‬ ‫ﻣﺜﺎﻝ: ﻗﺎﻧﻮﻥ )٦١( ﺭﺍ ﺑﺎ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﻗﻀﻴﻪ ﺩﻣﻮﺭﮔﺎﻥ ﺍﺛﺒﺎﺕ ﻛﻨﻴﺪ.‬ ‫)31(‬ ‫) ‪( A + B) . ( A + C ) = ( A + B) . ( A + C ) = ( A + B) + ( A + C‬‬ ‫)31(‬ ‫)41(‬ ‫)51(‬ ‫) ‪= A B + A C = A(B + C ) = A + (B + C‬‬ ‫)41(‬ ‫‪= A + B C = A + BC‬‬ ‫ﻣﺜﺎﻝ: ﻗﺎﻧﻮﻥ )٧١( ﺭﺍ ﺑﺎ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﻗﻀﻴﻪ ﺩﻣﻮﺭﮔﺎﻥ ﺛﺎﺑﺖ ﻧﻤﺎﻳﻴﺪ.‬ ‫)31(‬ ‫) ‪A + AB = A + AB = A + A + B = A + (A + B‬‬ ‫)51(‬ ‫)41(‬ ‫‪= A .( A + B ) = A. A + A B‬‬ ‫۰‬ ‫)31(‬ ‫‪AB = A + B‬‬ ‫4-4‐ﻃﺮﺍﺣﻲ ﻣﺪﺍﺭﻫﺎﻱ ﻣﻨﻄﻘﻲ ﺗﺮﻛﻴﺒﻲ)‪(Combinational Logic Design‬‬ ‫ﺩﺭ ﻃﺮﺍﺣﻲ ﻣﺪﺍﺭﻫﺎﻱ ﻣﻨﻄﻘﻲ ﺗﺮﻛﻴﺒﻲ، ﻫﺪﻑ ﻃﺮﺍﺣﻲ “ﺳﺎﺩﻩﺗﺮﻳﻦ” ﻣﺪﺍﺭ ﻣﻤﻜﻦ ﺟﻬﺖ ﺩﺳﺘﻴﺎﺑﻲ ﺑﻪ ﻳﻚ ﺭﻓﺘﺎﺭ‬ ‫ﻣﺸﺨﺺ ﻭﺭﻭﺩﻱ ﺧﺮﻭﺟﻲ ﻣﻲﺑﺎﺷﺪ، ﺑﻨﺤﻮﻳﻜﻪ ﻣﺪﺍﺭ ﻣﻮﺭﺩﻧﻈﺮ ﺑﺘﻮﺍﻧﺪ ﺩﺭ ﺍﺯﺍﺀ ﻫﺮ ﺗﺮﻛﻴﺐ ﻣﺸﺨﺺ ﺍﺯ ﻭﺭﻭﺩﻱﻫﺎ،‬ ‫ﺗﺮﻛﻴﺐ ﻣﻄﻠﻮﺏ ﺧﺮﻭﺟﻲﻫﺎ ﺭﺍ ﺗﻮﻟﻴﺪ ﻧﻤﺎﻳﺪ.‬ ‫ﻣﺮﺍﺣﻞ ﻃﺮﺍﺣﻲ ﻣﺪﺍﺭﻫﺎﻱ ﻣﻨﻄﻘﻲ ﺗﺮﻛﻴﺒﻲ ﺑﻄﻮﺭ ﺧﻼﺻﻪ ﺷﺎﻣﻞ ﻣﺮﺍﺣﻞ ﺯﻳﺮ ﺍﺳﺖ.‬ ‫1ﺗﺸﺮﻳﺢ ﻋﻤﻠﻜﺮﺩ ﻣﻄﻠﻮﺏ ﺳﻴﺴﺘﻢ )ﺍﺯ ﻧﻈﺮ ﺭﻓﺘﺎﺭ ﻭﺭﻭﺩﻱ ﺧﺮﻭﺟﻲ(‬‫2ﺗﺸﻜﻴﻞ ﺟﺪﻭﻝ ﺭﺍﺳﺘﻲ )‪ (Truth Table‬ﻳﺎ ﺟﺪﻭﻝ ﻛﺎﺭﻧﻮ‬‫3ﺑﺪﺳﺖﺁﻭﺭﺩﻥ ﻳﻚ ﻋﺒﺎﺭﺕ ﺑﻮﻟﻲ ﺑﺮﺍﻱ ﻫﺮ ﻳﻚ ﺍﺯ ﺧﺮﻭﺟﻲﻫﺎ ﺑﺼﻮﺭﺕ ﺗﺎﺑﻌﻲ ﺍﺯ ﻭﺭﻭﺩﻱﻫﺎ‬‫4ﺳﺎﺩﻩﺳﺎﺯﻱ ﻋﺒﺎﺭﺕ ﺑﺪﺳﺖﺁﻣﺪﻩ ﺩﺭ ﻣﺮﺣﻠﻪ ٣ )ﺩﺭ ﺻﻮﺭﺕ ﻧﻴﺎﺯ(‬‫5ﻃﺮﺍﺣﻲ ﻣﺪﺍﺭ ﻣﻨﻄﻘﻲ ﺑﺮﺍﺳﺎﺱ ﻋﺒﺎﺭﺍﺕ ﺳﺎﺩﻩ ﺷﺪﻩ‬‫ﻣﺜﺎﻝ: ﺩﺭ ﺳﻴﺴﺘﻢ ﻛﻨﺘﺮﻝ ﺳﻄﺢ ﺁﺏ ﺗﺎﻧﻚ ﺍﻫﺪﺍﻑ ﺯﻳﺮ ﻣﺪﻧﻈﺮ ﺍﺳﺖ:‬ ‫۱‐ ﺗﺸﺮﻳﺢ ﻋﻤﻠﻜﺮﺩ ﻣﻄﻠﻮﺏ ﺳﻴﺴﺘﻢ:‬ ‫• ﺍﮔﺮ ﺳﻄﺢ ﺁﺏ ”‪ “Very low‬ﺑﺎﺷﺪ ﻫﺮ ﺩﻭ ﺷﻴﺮ 1‪ V‬ﻭ 2‪ V‬ﺑﺎﺯ ﮔﺮﺩﻧﺪ.‬ ‫• ﺍﮔﺮ ﺳﻄﺢ ﺁﺏ ”‪ “Low‬ﺑﺎﺷﺪ ﻓﻘﻂ ﺷﻴﺮ 2‪ V‬ﺑﺎﺯ ﺑﺎﺷﺪ.‬ ‫• ﺍﮔﺮ ﺳﻄﺢ ﺁﺏ ”‪ “Desired level‬ﺑﺎﺷﺪ ﻓﻘﻂ ﺷﻴﺮ 1‪ V‬ﺑﺎﺯ ﺑﺎﺷﺪ.‬ ‫• ﺍﮔﺮ ﺳﻄﺢ ﺁﺏ ”‪ “High‬ﺑﺎﺷﺪ ﻫﺮ ﺩﻭ ﺷﻴﺮ ﺑﺴﺘﻪ ﺑﺎﺷﺪ.‬ ‫• ﺧﺮﺍﺑﻲ ﺳﻨﺴﻮﺭﻫﺎﻱ ‪ A ، B‬ﻳﺎ ‪ C‬ﺗﻮﺳﻂ ﺳﻴﮕﻨﺎﻝ‪Fault‬‬ ‫2‪V‬‬ ‫١‪V‬‬ ‫ﺍﻋﻼﻡ ﮔﺮﺩﻳﺪﻩ ﻭ ﺩﺭ ﺻﻮﺭﺕ ﺧﺮﺍﺑﻲ ﻫﺮﺩﻭ ﺷﻴﺮ ﺑﺴﺘﻪ ﮔﺮﺩﻧﺪ.‬ ‫‪High‬‬ ‫‪A‬‬ ‫‪B‬‬ ‫‪C‬‬ ‫‪Logic‬‬ ‫‪Fault‬‬ ‫‪warning‬‬ ‫‪Desired Level‬‬ ‫‪Low‬‬ ‫‪F‬‬ ‫‪Very Low‬‬ ‫۲‐ ﺗﺸﻜﻴﻞ ﺟﺪﻭﻝ ﺭﺍﺳﺘﻲ:‬ ‫ﺷﺮﺍﻳﻂ ﺧﺮﻭﺟﻲ‬ ‫ﻫﺮ ﺩﻭ ﺷﻴﺮ ﺑﺎﺯ‬ ‫ﺷﻴﺮ 2‪ V‬ﺑﺎﺯ‬ ‫ﻫﺮ ﺩﻭ ﺷﻴﺮ ﺑﺴﺘﻪ‬ ‫ﺷﻴﺮ ﺑﺎﺯ 1‪V‬‬ ‫ﻫﺮ ﺩﻭ ﺷﻴﺮ ﺑﺴﺘﻪ‬ ‫ﻫﺮ ﺩﻭ ﺷﻴﺮ ﺑﺴﺘﻪ‬ ‫ﻫﺮ ﺩﻭ ﺷﻴﺮ ﺑﺴﺘﻪ‬ ‫ﻫﺮ ﺩﻭ ﺷﻴﺮ ﺑﺴﺘﻪ‬ ‫‪Fault‬‬ ‫٠‬ ‫٠‬ ‫١‬ ‫۰‬ ‫١‬ ‫١‬ ‫١‬ ‫٠‬ ‫2‪V‬‬ ‫1‪V‬‬ ‫‪C‬‬ ‫١‬ ‫١‬ ‫٠‬ ‫۰‬ ‫٠‬ ‫٠‬ ‫٠‬ ‫٠‬ ‫١‬ ‫٠‬ ‫٠‬ ‫1‬ ‫٠‬ ‫٠‬ ‫٠‬ ‫٠‬ ‫٠‬ ‫١‬ ‫٠‬ ‫1‬ ‫٠‬ ‫١‬ ‫٠‬ ‫١‬ ‫‪B‬‬ ‫٠‬ ‫٠‬ ‫١‬ ‫1‬ ‫٠‬ ‫٠‬ ‫١‬ ‫١‬ ‫‪A‬‬ ‫‪Condition‬‬ ‫۰‬ ‫٠‬ ‫٠‬ ‫۰‬ ‫١‬ ‫١‬ ‫١‬ ‫١‬ ‫‪Very low‬‬ ‫‪Low‬‬ ‫‪Fault‬‬ ‫.‪o.k‬‬ ‫‪Fault‬‬ ‫‪Fault‬‬ ‫‪Fault‬‬ ‫‪High‬‬ ‫۳‐ ﺑﺪﺳﺖ ﺁﻭﺭﺩﻥ ﻳﻚ ﻋﺒﺎﺭﺕ ﺑﻮﻟﻲ ﺑﺮﺍﻱ ﻫﺮﻳﻚ ﺍﺯ ﺳﻪ ﺧﺮﻭﺟﻲ 2‪ V1 ، V‬ﻭ ) F‬ﺩﺭ ﺍﻳﻨﺠﺎ ﻓﻘﻂ ﻳﻜﻲ ﺍﺯ‬ ‫ﺳﻪ ﺧﺮﻭﺟﻲ ﻳﻌﻨﻲ ‪ F‬ﺭﺍ ﺩﺭﻧﻈﺮ ﮔﺮﻓﺘﻪ ﻭ ﺩﻧﺒﺎﻝ ﻣﻲﻧﻤﺎﻳﻴﻢ(‬ ‫‪F = A B C + A B C + A B C + AB C‬‬ ‫۴‐ ﺳﺎﺩﻩﺳﺎﺯﻱ ﻋﺒﺎﺭﺕ ﺑﺪﺳﺖﺁﻣﺪﻩ ﺩﺭ ﻣﺮﺣﻠﻪ ٣‬ ‫)51(‬ ‫) ‪F = ( A + A) BC + AB (C + C‬‬ ‫)5 (‬ ‫‪F = BC + AB‬‬ ‫‪ABC‬‬ ‫‪A BC‬‬ ‫‪ABC‬‬ ‫‪ABC‬‬ ‫‪F‬‬ ‫0‬ ‫0‬ ‫1‬ ‫0‬ ‫1‬ ‫1‬ ‫1‬ ‫0‬ ‫‪C‬‬ ‫0‬ ‫1‬ ‫0‬ ‫1‬ ‫0‬ ‫1‬ ‫0‬ ‫1‬ ‫‪B‬‬ ‫0‬ ‫0‬ ‫1‬ ‫1‬ ‫0‬ ‫0‬ ‫1‬ ‫1‬ ‫‪A‬‬ ‫0‬ ‫0‬ ‫0‬ ‫0‬ ‫1‬ ‫1‬ ‫1‬ ‫1‬ ‫• ﺍﻟﺒﺘﻪ ﺩﺭ ﺻﻮﺭﺕ ﺩﺳﺘﺮﺳﻲ ﺑﻪ ﻛﺎﻣﭙﻴﻮﺗﺮ، ﻣﻲﺗﻮﺍﻥ ﺑﺎ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﻧﺮﻡﺍﻓﺰﺍﺭ ‪ Maple‬ﺳﺎﺩﻩﺳﺎﺯﻱﻫﺎﻱ‬ ‫ﭘﻴﭽﻴﺪﻩﺗﺮ ﺭﺍ ﺍﻧﺠﺎﻡ ﺩﺍﺩ. ﻧﻤﻮﻧﻪﻫﺎﻳﻲ ﺍﺯ ﻛﺎﺭﺑﺮﺩ ﺍﻳﻦ ﻧﺮﻡﺍﻓﺰﺍﺭ ﺩﺭ ﺻﻔﺤﻪ ﺑﻌﺪ ﺁﻣﺪﻩ ﺍﺳﺖ:‬ >with (logic); [bequal, bsimp, canon, convert/MOD2, convert/ forminert, convert/toinert, distrib, dual, environ, randbool, satisfy, tautology] >bsimp (a &or (a &and b)); a a + (a .b) → a >bsimp (a &or ((&not a) &and b)); a &or b a + (a .b ) → a + b >bsimp (&or(&and(a, b), &and(a, c, d), &and(a, &not (c)), &and(a, &not(d)), e )); a &or e ( a . b + acd + a c + a d + e ) → a + e >bsimp (&and (&or(a, b, c), &or(a, &not(b), &not(c)), &or(a, &not(b), c) )); a &or (c &and &not (b)) [( a + b + c ) . ( a + b + c ) . ( a + b + c )] → a + ( c . b ) ‫ﺍﺯ ﺟﻤﻠﻪ ﺭﻭﺵﻫﺎﻱ ﺳﻴﺴﺘﻤﺎﺗﻴﻚ ﺑﺮﺍﻱ ﺳﺎﺩﻩﺳﺎﺯﻱ ﻋﺒﺎﺭﺍﺕ ﺑﻮﻟﻲ، ﺭﻭﺵﻫﺎﻳﻲ ﺗﺤﺖ ﻋﻨﻮﺍﻥ‬ ‫”‪“Simplifications using prime implicants‬ﻣﻲﺑﺎﺷﻨﺪ. ﻳﻜﻲ ﺍﺯ ﺍﻳﻦ ﺭﻭﺵﻫﺎ ﺩﺭ ﻛﺘﺎﺏ‬ ‫)‪“Logical Design of Automation systems‬ﻧـــﻮﺷﺘــــﺔ ‪Sander B. Friedman‬‬ ‫)ﺻﻔﺤﺎﺕ٣٤ ﺍﻟﻲ١٥( ﺁﻣﺪﻩ ﺍﺳﺖ. ﻫﺪﻑ ﺩﺭ ﺍﻳﻦ ﺭﻭﺵ ﻳﺎﻓﺘﻦ ﻗﺮﻳﻨﻪﺍﻱ ﻣﺘﺒﺎﻳﻦ ﺑﺮﺍﻱ ﻋﺒﺎﺭﺕ ﺑﻮﻟـﻲﺩﺍﺩﻩ‬ ‫ﺷﺪﻩ ﺍﺳﺖ ﺑﻨﺤﻮﻳﻜﻪ ﺍﮔﺮ ﻳﻚ ﺟﻤﻠﻪ ﻳﺎ ‪) Literal‬ﻣﺘﻐﻴﺮ ﺑﻮﻟﻲ( ﺩﻳﮕﺮ ﺍﺯ ﻋﺒﺎﺭﺕ ﻗﺮﻳﻨﻪ ﻣﺘﺒــﺎﻳﻦ ﺣــﺬﻑ‬ ‫ﮔﺮﺩﺩ، ﺩﻳﮕﺮ ﻋﺒﺎﺭﺕ ﻣﺰﺑﻮﺭ ﺑﺎ ﻋﺒﺎﺭﺕ ﺍﻭﻟﻴﻪ ﻣﻌﺎﺩﻝ ﻧﺒﺎﺷﺪ. . . .‬ ‫۵‐ ﻃﺮﺍﺣﻲ ﻣﺪﺍﺭ ﻣﻨﻄﻘﻲ ﺑﺮﺍﺳﺎﺱ ﻋﺒﺎﺭﺕ ﺳﺎﺩﻩ ﺷﺪﻩ ﺩﺭ ﻣﺮﺣﻠﻪ ٤‬ ‫‪F = BC + AB‬‬ ‫‪AB‬‬ ‫‪F‬‬ ‫+‬ ‫‪A‬‬ ‫‪B‬‬ ‫‪B‬‬ ‫‪BC‬‬ ‫‪C‬‬ ‫‪C‬‬ ‫• ﺟﺪﻭﻝ ﻛﺎﺭﻧﻮ )‪ (Karnaugh map‬ﻫﻤﺎﻥ ﺍﻃﻼﻋﺎﺗﻲ ﺭﺍ ﻛﻪ ﺩﺭ ﺟﺪﻭﻝ ﺭﺍﺳﺘﻲ ﻭﺟﻮﺩ ﺩﺍﺭﺩ ﺑﺸﻜﻠﻲ ﻣﺘﻔﺎﻭﺕ‬ ‫ﻧﺸﺎﻥ ﻣﻲﺩﻫﺪ. ﺩﺭ ﺟﺪﻭﻝ ﻛﺎﺭﻧﻮ، ﻣﺘﻐﻴﺮﻫﺎﻱ ﻭﺭﻭﺩﻱ ‪ A ، B‬ﻭ ‪ ) C‬ﺩﺭ ﻣﺜﺎﻝ ﻗﺒﻞ( ﺑﺎ ﺗﺮﺗﻴﺒﻲ ﺧﺎﺹ‬ ‫)ﺑﺮﺍﺳﺎﺱ ‪ ( Gray code‬ﺩﺭ ﺳﻄﺮﻫﺎ ﻭ ﺳﺘﻮﻥﻫﺎﻱ ﺟﺪﻭﻝ ﻗﺮﺍﺭ ﻣﻲﮔﻴﺮﻧﺪ:‬ ‫ﺭﻗﻢ ﺳﻮﻡ‬ ‫• ﺩﺭ ﻛﺪ ،‪ binary‬ﺗﺮﺗﻴﺐ ﺍﻋﺪﺍﺩ ﺑﻨﺤﻮﻳﺴﺘﻜﻪ ﻫﺮ ﻋﺪﺩ ﺑﺎ ﻋﺪﺩ ﺑﻌﺪﻱ ﺍﺯﻧﻈﺮ ﺷﻤﺎﺭﺵ ﻳﻜﻲ‬ ‫ﻓﺎﺻﻠﻪ ﺩﺍﺷﺘﻪ ﺑﺎﺷﺪ:‬ ‫011‬ ‫{‬ ‫111‬ ‫{‬ ‫7‬ ‫101‬ ‫{‬ ‫6‬ ‫001‬ ‫{‬ ‫4‬ ‫5‬ ‫110‬ ‫{‬ ‫3‬ ‫ﺭﻗﻢ ﺩﻭﻡ‬ ‫ﺭﻗﻢ ﺍﻭﻝ‬ ‫010‬ ‫{‬ ‫2‬ ‫100‬ ‫{‬ ‫1‬ ‫000‬ ‫{‬ ‫0‬ ‫• ﺍﻣﺎ ﺩﺭ ﻛﺪ ‪ Gray‬ﺗﺮﺗﻴﺐ ﺍﻋﺪﺍﺩ ﺑﻨﺤﻮﻳﺴﺘﻜﻪ ﻫﺮ ﻋﺪﺩ ﺑﺎ ﻋﺪﺩ ﺑﻌﺪﻱ )ﻳﺎ ﺩﻭ ﻋﺪﺩ ﻣﺠﺎﻭﺭ( ﻓﻘﻂ ﺩﺭ ﻳﻚ ﺭﻗﻢ )١ ﺑﻴﺖ(‬ ‫ﺑﺎ ﻫﻢ ﻣﺘﻔﺎﻭﺕ ﻣﻲﺑﺎﺷﻨﺪ:‬ ‫001 101 111 011 010 110 100 000 : ‪Right gray code‬‬ ‫{{‬ ‫{‬ ‫{‬ ‫{{{‬ ‫{‬ ‫4‬ ‫5‬ ‫7‬ ‫6‬ ‫2‬ ‫100‬ ‫{‬ ‫101‬ ‫{‬ ‫111‬ ‫{‬ ‫110‬ ‫{‬ ‫010‬ ‫{‬ ‫1‬ ‫5‬ ‫7‬ ‫3‬ ‫2‬ ‫3‬ ‫011‬ ‫{‬ ‫6‬ ‫1‬ ‫001‬ ‫{‬ ‫4‬ ‫0‬ ‫000‬ ‫{‬ ‫: ‪Left gray code‬‬ ‫0‬ ‫ﺩﺭ ،‪ Right gray code‬ﺭﻗﻢ ﺳﻤﺖ ﺭﺍﺳﺖ ﺳﺮﻳﻌﺘﺮ ﺗﻐﻴﻴﺮ ﻣﻲﻧﻤﺎﻳﺪ ﺍﻣﺎ ﺩﺭ ‪ Left gray code‬ﺭﻗﻢ ﺳﻤﺖ ﭼﭗ‬ ‫ﺳﺮﻳﻌﺘﺮ ﺗﻐﻴﻴﺮ ﻣﻲﻛﻨﺪ. ﺍﺯ ﻃﺮﻓﻲ ﺩﺭ ﻣﻘﺎﻳﺴﻪ ﺑﺎ ﻛﺪ ‪ binary‬ﺳﺮﻳﻌﺘﺮﻳﻦ ﺭﻗﻢ ﺗﻐﻴﻴﺮ ﻛﻨﻨﺪﻩ، ﺩﻭ ﻋﺪﺩ ﺩﻭ ﻋﺪﺩ ﺗﻐﻴﻴﺮ‬ ‫ﻣﻲﻧﻤﺎﻳﺪ.‬ ‫‪Gray code‬‬ ‫‪Binary code‬‬ ‫000‬ ‫100‬ ‫000‬ ‫100‬ ‫110‬ ‫010‬ ‫010‬ ‫011‬ ‫110‬ ‫001‬ ‫111‬ ‫101‬ ‫101‬ ‫001‬ ‫011‬ ‫111‬ ‫ﺗﻐﻴﻴﺮ ﺳﺮﻳﻌﺘﺮ ﺭﻗﻢ ﺳﻤﺖ ﺭﺍﺳﺖ‬ ‫ﻳﻜﻲ ﺍﺯ ﻣﺸﺨﺼﻪﻫﺎﻱ ﻣﻬﻢ ‪ Gray code‬ﺁﻧﺴﺘﻜﻪ ﺩﺭ ﻳﻚ ﻣﺠﻤﻮﻋﻪ ﺍﻋﺪﺍﺩ ‪ n‬ﺑﻴﺘﻲ ﻫﻤﻮﺍﺭﻩ ﺍﻭﻟﻴﻦ ﻋﺪﺩ ﻭ ﺁﺧﺮﻳﻦ‬ ‫ﻋﺪﺩ )ﻣﺎﻧﻨﺪ ٠٠٠ ﻭ ٠٠١ ﺩﺭ ﻣﺠﻤﻮﻋﻪ ﺍﻋﺪﺍﺩ ﺳﻪ ﺑﻴﺘﻲ ﺑﺮﺍﺳﺎﺱ ‪ ( Right gray code‬ﻣﺠﺎﻭﺭ ﻣﺤﺴﻮﺏ ﻣﻲﺷﻮﻧﺪ‬ ‫ﺯﻳﺮﺍ ﻛﻪ ﺍﻭﻟﻴﻦ ﻭ ﺁﺧﺮﻳﻦ ﻋﺪﺩ ﻫﻢ ﻓﻘﻂ ﺩﺭ ﻳﻚ ﺑﻴﺖ ﺑﺎﻫﻢ ﺗﻔﺎﻭﺕ ﺩﺍﺭﻧﺪ.‬ ‫• ﺩﺭ ﺍﺷﻜﺎﻝ ﺯﻳﺮ ﺟﺪﻭﻝ ﻛﺎﺭﻧﻮ ﺑﺮﺍﻱ ﺳﻴﺴﺘﻢﻫﺎﻳﻲ ﺑﺎ ٢، ٣، ٤ ﻭ ٥ ﻣﺘﻐﻴﺮ ﻭﺭﻭﺩﻱ ﻧﺸﺎﻥ ﺩﺍﺩﻩ ﺷﺪﻩ ﺍﺳﺖ.‬ ‫‪AB‬‬ ‫01‬ ‫11‬ ‫10‬ ‫‪A‬‬ ‫ﺗﺮﺗﻴﺐ‪: Gray Code‬‬ ‫00‬ ‫0‬ ‫1‬ ‫1‬ ‫0‬ ‫1‬ ‫‪C‬‬ ‫ﺳﻪ ﻣﺘﻐﻴﺮ ﻭﺭﻭﺩﻱ: ‪A، B، C‬‬ ‫‪B‬‬ ‫ﺩﻭ ﻣﺘﻐﻴﺮ ﻭﺭﻭﺩﻱ‬ ‫ﺗﺮﺗﻴﺐ‪: Gray Code‬‬ ‫‪ABC‬‬ ‫‪AB‬‬ ‫101 111 011 010 110 100 000‬ ‫00‬ ‫10‬ ‫11‬ ‫01‬ ‫ﭘﻨﺞ ﻣﺘﻐﻴﺮ ﻭﺭﻭﺩﻱ: ‪A, B, C, D, E‬‬ ‫0‬ ‫01‬ ‫‪DE‬‬ ‫11‬ ‫10‬ ‫00‬ ‫00‬ ‫10‬ ‫11‬ ‫01‬ ‫ﭼﻬﺎﺭ ﻣﺘﻐﻴﺮ ﻭﺭﻭﺩﻱ: ‪A, B, C, D‬‬ ‫‪CD‬‬ ‫• ﺩﺭﻭﻥ ﺧﺎﻧﻪﻫﺎﻱ ﺟﺪﻭﻝ ﻛﺎﺭﻧﻮ، ﺗﻮﺳﻂ ﻭﺿﻌﻴﺖ ﺧﺮﻭﺟﻲ )ﻓﻘﻂ ﻳﻚ ﺧﺮﻭﺟﻲ( ﭘﺮ ﻣﻲﺷﻮﺩ‬ ‫ﺑﺮﺍﻱ ﻣﺜﺎﻝ ﻗﺒﻠﻲ ﺟﺪﻭﻝ ﺭﺍﺳﺘﻲ ﻭ ﻛﺎﺭﻧﻮ ﺩﺭ ﺯﻳﺮ ﺁﻭﺭﺩﻩ ﺷﺪﻩ ﺍﺳﺖ.‬ ‫‪C Fault‬‬ ‫0‬ ‫0‬ ‫1‬ ‫0‬ ‫0‬ ‫1‬ ‫1‬ ‫0‬ ‫0‬ ‫1‬ ‫1‬ ‫1‬ ‫0‬ ‫1‬ ‫1‬ ‫0‬ ‫‪AB‬‬ ‫01‬ ‫1‬ ‫1‬ ‫11‬ ‫1‬ ‫0‬ ‫10‬ ‫1‬ ‫0‬ ‫00‬ ‫0‬ ‫0‬ ‫0‬ ‫1‬ ‫‪C‬‬ ‫ﺟﺪﻭﻝ ﻛﺎﺭﻧﻮ ﺑﺮﺍﻱ ﺳﻴﮕﻨﺎﻝ ‪Fault‬‬ ‫‪B‬‬ ‫0‬ ‫0‬ ‫1‬ ‫1‬ ‫0‬ ‫0‬ ‫1‬ ‫1‬ ‫‪A‬‬ ‫0‬ ‫0‬ ‫0‬ ‫0‬ ‫1‬ ‫1‬ ‫1‬ ‫1‬ ‫ﺑﺎ ﺗﻮﺟﻪ ﺑﻪ ﻣﺜﺎﻝ ﻓﻮﻕ، ﻣﺰﻳﺖ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﻛﺪ ‪ Gray‬ﺭﻭﺷﻦ ﻣﻲﺷﻮﺩ. ﺧﺎﻧﻪﻫﺎﻱ ﻣﺠﺎﻭﺭﻱ ﻛﻪ ﺩﺭ ﺟﺪﻭﻝ ﻛﺎﺭﻧﻮ ﺑﺎ “١”‬‫ﭘﺮ ﺷﺪﻩﺍﻧﺪ ﺑﺮﺍﺣﺘﻲ ﺑﻔﺮﻡ ﺳﺎﺩﻩ ﺷﺪﻩ ﻗﺎﺑﻞ ﺍﺳﺘﺨﺮﺍﺝ ﻫﺴﺘﻨﺪ:‬ ‫‪AB‬‬ ‫‪C A B + C AB = C B ( A + A) = C B‬‬ ‫321‬ ‫44‬ ‫1‬ ‫‪C A B + CA B = (C + C ) A B = A B‬‬ ‫۱‬ ‫01‬ ‫1‬ ‫1‬ ‫11‬ ‫1‬ ‫0‬ ‫10‬ ‫1‬ ‫0‬ ‫00‬ ‫0‬ ‫0‬ ‫0‬ ‫1‬ ‫ﺑﺎ ﺗﻮﺟﻪ ﺑﻪ ﺍﻳﻨﻜﻪ ﺧﺎﻧﻪﻫﺎﻱ ﻣﺠﺎﻭﺭ ﺩﺭ ﺟﺪﻭﻝ ﻛﺎﺭﻧﻮ ﻓﻘﻂ ﺩﺭ ﻳﻚ ‪ bit‬ﺑﺎ ﻫﻢ ﺗﻔﺎﻭﺕ ﺩﺍﺭﻧﺪ، ﻭﺭﻭﺩﻱ ﻣﺘﻨﺎﻇﺮ ﺑﺎ ‪ bit‬ﻣﺰﺑﻮﺭ ﺭﺍ‬ ‫)ﺑﺎ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﻗﺎﻧﻮﻥ ﺟﺒﺮ ﺑﻮﻟﻲ ﺷﻤﺎﺭﻩ )٥( ﺩﺭ ﺑﺨﺶ ٤‐٣‐٢( ﻣﻲﺗﻮﺍﻥ ﺍﺯ ﻋﺒﺎﺭﺕ ﺩﺭﺑﺮﮔﻴﺮﻧﺪﻩ ﺧﺎﻧﻪﻫﺎﻱ ﻣﺠﺎﻭﺭ ﺣﺬﻑ‬ ‫ﻧﻤﻮﺩ . . . . ﻣﺎﻧﻨﺪ ﺣﺬﻑ ‪ A‬ﻭ ‪ C‬ﺍﺯ ﻋﺒﺎﺭﺍﺕ ﺑﺪﺳﺖ ﺁﻣﺪﻩ ﺩﺭ ﻣﺜﺎﻝ ﻓﻮﻕ.‬ ‫‪C‬‬ AB 00 01 11 10 00 1 1 0 0 CD 01 1 1 1 0 ABD A BC ABC 11 0 0 1 1 :‫ﻣﺜﺎﻝ‬ AC ( B + B ) = AC CD 10 0 0 0 0 00 0 1 1 0 00 01 11 10 AB 01 1 0 0 1 11 1 0 0 1 BD ACD Z = BD + B D Z = A C + ABD + ACD CD AB 00 01 11 10 00 1 1 1 1 CD 01 0 1 1 0 11 0 1 1 0 BD Z = C D + BD + B C D 10 1 0 0 1 BC D 10 0 1 1 0 BD ‫⇐ ﺩﺭ ﺗﺸﻜﻴﻞ ﮔﺮﻭﻩﻫﺎﻱ ﻧﺸﺎﻥ ﺩﺍﺩﻩ ﺷﺪﻩ )ﺍﺯ 1 ﻫﺎ(، ﺍﻭﻻ ﮔﺮﻭﻩﻫﺎ ﺑﺎﻳﺪ ﻣﺮﺑﻊ ﻣﺴﺘﻄﻴﻞ ﺷﻜﻞ ﺑﻮﺩﻩ ﻭ ﺷﺎﻣﻞ١، ٢، ٤، ٨ ،‬ ‫ﹰ‬ ‫… ﺧﺎﻧﻪ ﺑﺎﺷﻨﺪ. ﺿﻤﻨﺎ ﺑﺎﻳﺪ ﺳﻌﻲ ﻧﻤﻮﺩ ﻛﻪ ﻫﺮ ﻳﻚ ﺍﺯ ﮔﺮﻭﻩﻫﺎ ﺭﺍ ﺗﺎ ﺣﺪ ﻣﻤﻜﻦ ﺑﺰﺭﮔﺘﺮ ﺍﻧﺘﺨﺎﺏ ﻧﻤﻮﺩ.‬ ‫ﹰ‬ ‫ﭼﻨﺪ ﻧﻜﺘﻪ ﺩﺭ ﻣﻮﺭﺩ ﻃﺮﺍﺣﻲ ﺳﻴﺴﺘﻢﻫﺎﻱ ﻣﻨﻄﻘﻲ ﺗﺮﻛﻴﺒﻲ‬ ‫۱‐ ﺗﺸﻜﻴﻞ ﻓﺮﻡ ‪ POS‬ﺍﺯ ﺟﺪﻭﻝ ﺭﺍﺳﺘﻲ ﺻﻔﺤﻪ ٥٩ ﻛﺘﺎﺏ‪Digital Electronics: D. C. Green‬‬ ‫۲‐ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﻓﺮﻡ ﻣﻌﻜﻮﺱ ﺟﻬﺖ ﺳﺎﺩﻩﺳﺎﺯﻱ ﻋﺒﺎﺭﺍﺕ ﻣﻨﻄﻘﻲ ﺩﺭ ﺟﺪﻭﻝ ﻛﺎﺭﻧﻮ: ﺹ٢١١ﻛﺘﺎﺏ‪D.C.Green‬‬ ‫۳‐ ﺗﺸﻜﻴﻞ ﻓﺮﻡ ‪ POS‬ﺍﺯ ﺟﺪﻭﻝ ﻛﺎﺭﻧﻮ ﺻﻔﺤﻪ ٤١١ ﻛﺘﺎﺏ‪D. C. Green‬‬ ‫۴‐ ﺗﺸﻜﻴﻞ ﻣﺪﺍﺭﻫﺎﻱ ﻣﻨﻄﻘﻲ ﺑﺎ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ‪ NAND gates‬ﺹ٦٢١ﻭ ﺹ٣٣١ ﻛﺘﺎﺏ‪D.C.Green‬‬ ‫۵‐ ﺗﺸﻜﻴﻞ ﻣﺪﺍﺭﻫﺎﻱ ﻣﻨﻄﻘﻲ ﺑﺎ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ‪ NOR‬ﺹ ٦٢١ ﻭ ﺹ ٦٣١ ﻛﺘﺎﺏ‪D.C.Green‬‬ ...
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