Homework%208%20solutions

Homework%208%20solutions - Homework #8, NOT due Thursday...

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I. (25%) An n + polysilicon-gate p-channel MOS transistor is made on an n-type Si Substrate with N d = 5 x 10 16 /cm 3 . The SiO 2 thickness is 10 nm in the gate region, and the effective interface charge is 2 x 10 11 /cm 2 . Sketch the C-V curve for this device showing the values of threshold and flatband voltages and the minimum and maximum capacitances. Fig. 6-17 may be helpful. V 293 . 0 cm / F 10 45 . 3 ) / Coulombs 10 602 . 1 )( cm / 10 2 ( V 2 . 0 2 7 19 2 11 q C Q V i i ms FB V 402 . 1 cm / F 10 45 . 3 cm / Coulombs 10 144 . 1 V 788 . 0 2 2 7 2 7 FB i d ms T V C Q V 2 8 6 14 cm / F 10 30 . 7 cm 10 cm) / F 10 85 . 8 )( 8 . 11 ( m d W C 2 8 2 8 2 7 2 8 2 7 cm / F 10 03 . 6 cm / F 10 30 . 7 cm / F 10 45 . 3 ) cm / F 10 30 . 7 )( cm / F 10 45 . 3 ( d
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Homework%208%20solutions - Homework #8, NOT due Thursday...

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