3 - EE 330 Homework Assignment 3 Fall 2007 Problem 1 The...

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EE 330 Homework Assignment 3 Fall 2007 Problem 1 The stick diagram of a circuit is shown. Give a circuit schematic for this circuit. The color-code for the stick diagram is shown to the right. p-active n-active Poly 1 Metal 1 n-well contact Problem 2 A stick diagram has been put together for a 3-input CMOS NAND gate and is shown below. There are one or more errors in this stick diagram. Identify and correct all errors in the stick diagram. The color-code for the stick diagram is shown in Problem 1.
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Problem 3 Draw a stick diagram for the cascade of the two CMOS gates shown. Problem 4 (weighted as 3 problems) Provide a layout of the following circuit with the goal of minimizing the total area of a square enclosing the layout of the circuit. Use the AMI 0.5u CMOS process. All electrical connections should exit the layout in Metal 1 and there should be no DRC violations. What is the overhead factor (Total circuit area divided by gate area) for your circuit? Your score for this problem will be based upon how small of a total area you achieve without violating any design rules.
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