ENGRI1110_Lect7_Sept11_09_posted - 50 nanometer Pt/TiOx/Pt...

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50 nanometer Pt/TiOx/Pt devices -200 -100 0 100 200 Current ( uA ) -2 -1 0 1 2 Voltage ( V ) 4 2 0 ( nA ) -2 -1 0 1 2 Voltage ( V ) a b Virgin I-V c 50 nm hp +V push O V  vacancies -V attract O V  vacancies 10 -3 10 -6 10 -9 -1 0 1 Pt Pt TiO 2 TiO x V + - Switching I-V TiOx Pt TiO2 Pt
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Where Silicon can’t go 3 dimensional: stack crossbars on top of each other Nonvolatile memory          Power not needed to maintain memory          Read bit with small alternating current so bit is not changed Latch circuits: useful for connecting nanowires to the outside world
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Nano / Micro interface Want to access large number of nanowires with small  number of microwires.
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Communicate with the nanowires row selector memory grid selected column column Selector selected row k-bit address selected memory cell k-bit address
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Demultiplexer Interface
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This note was uploaded on 02/10/2010 for the course ENGRI 1110 at Cornell University (Engineering School).

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ENGRI1110_Lect7_Sept11_09_posted - 50 nanometer Pt/TiOx/Pt...

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