Lecture26 - ENGRD 2300 Introduction to Digital Logic Design...

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Lecture 26: 1 ENGRD 2300 Introduction to Digital Logic Design Feedback Sequential Circuits Fall 2009
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Lecture 26: Announcements Lab 7 Final report due Saturday, Dec 5 Last chance lab, Mon afternoon 1:25-4:25 First come/first served (shared with another class) Final exam Tuesday Dec 15, 7:00pm Phillips Hall 101 HW5 Solutions to be posted Mon, Dec 7 2
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Lecture 26: Announcements Office Hours This Fri, 1:30-3:00 Next Week, Mon, Wed, Fri, 11:00am – Noon By Appointment Blackboard Gradebook Contains significant/systematic errors! I will correct these ASAP 3
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Lecture 26: Readings Chapter 1, Sections 3.1-3.7 Sections 2.1–2.9 Section 4.1 – 4.4 Sections 5.1, 5.4 Sections 6.1 – 6.11 Sections 7.1-7.8, 7.13 Sections 8.1, 8.4 – 8.5, 8.7 – 8.9 Sections 9.1-9.4 Sections 6.3, 8.3, 9.5-9.6 Sections 7.9-7.10 4
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Lecture 26: 5 Feedback Sequential Circuits Examples D latch, S-R latch, D flip-flop, J-K flip-flop Has at least one feedback loop that hold a 0 or a 1 at all times (except during state transitions) Circuit behavior depends on both current inputs and values stored in loops Fundamental mode circuits Multiple inputs not allowed to change simultaneously Allows time for circuit to settle before changing again
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Lecture 26: 6 Next State Logic Output Logic Inputs Outputs Feedback loop (Mealy machine) We have no control over when a state changes; timing is just determined by propagation delays Feedback Sequential Circuits
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Lecture 26: 7 Feedback Sequential Circuit Analysis Problem is that circuit constantly changes its state relative to inputs and current state No well-defined place to carry out analysis of state transitions as in a clocked design Solution Break each feedback loop and add an artificial delay
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Lecture26 - ENGRD 2300 Introduction to Digital Logic Design...

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