Lecture25 - ENGRD 2300 Introduction to Digital Logic Design...

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Lecture 25 1 ENGRD 2300 Introduction to Digital Logic Design Programmable Logic Arrays Programmable Array Logic Devices Programmable Logic Devices Complex Programmable Logic Devices Field-Programmable Gate Arrays Fall 2009
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Lecture 25: Announcements Lab 7 (last one!) on Blackboard Final labs Nov 30, Dec 1 and 2 Final report due Saturday, Dec 5 Final exam Tuesday Dec 15, 7:00pm Phillips Hall 101 Prelim 2 has been graded HW5 has been posted Due Wed, Dec 2 Solutions to be posted Mon, Dec 7 2
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Lecture 25: Prelim 2 Average 77.1, Std Dev 14.4 Median 81 3 0 5 10 15 20 25 30 0-49 50-59 60-69 70-79 80-89 90-100
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Lecture 25: Readings Chapter 1, Sections 3.1-3.7 Sections 2.1–2.9 Section 4.1 – 4.4 Sections 5.1, 5.4 Sections 6.1 – 6.11 Sections 7.1-7.8, 7.13 Sections 8.1, 8.4 – 8.5, 8.7 – 8.9 Sections 9.1-9.4 Sections 6.3, 8.3, 9.5-9.6 (Today) Sections 7.9-7.10 (Thursday) 4
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Lecture 25: A Comparison Intel’s first chip the 8088, introduced in 1981 29,000 transistors Intel’s latest chip “Nehalem”, introduced last year 731 million transistors Mr Barton [Intel VP] equates the two by comparing the a city the size of Ithaca, N.Y., with the continent of Europe. “Ithaca is quite complex in it’s own right if you think of all that goes on. If we scale up the population to 730 million, we come to Europe as about the right size. Now take Europe and shrink it until it all fits in about the same land mass as Ithaca.” New York Times, Nov. 17, 2008, pg B3 5
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Lecture 25: 6 Programmable Logic Arrays (PLAs) Any combinational logic function can be realized as a sum of products Idea: Build a large AND-OR array with lots of inputs and product terms, and programmable connections n inputs AND gates have 2n inputs -- true and complement of each variable Each input can be removed from each AND gate m outputs, driven by large OR gates Each AND gate output is an input to each OR gate Each input can be removed from each OR gate p AND gates (p<<2 n )
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Lecture 25: 7 Example: 4x3 PLA, 6 Product Terms
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Lecture 25: 8 Compact Representation X’s mark locations of programmable connections
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Lecture25 - ENGRD 2300 Introduction to Digital Logic Design...

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