Lecture24

Lecture24 - ENGRD 2300 Introduction to Digital Logic Design...

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Lecture 24: 1 ENGRD 2300 Introduction to Digital Logic Design Pipelined Microprocessors Fall 2009
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Lecture 24 Announcements Lab 7 (last one!) on Blackboard Single cycle microprocessor Get an early start! Open labs Nov 23, and 24 Final labs Nov 30, Dec 1 and 2 Final report due Saturday, Dec 5 Lab partners? Final exam Tuesday Dec 15, 7:00pm Phillips Hall 101 Prelim 2 not graded HW5 to be posted by Wed 2
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Lecture 24 3 Control Hazards A control hazard occurs when instructions following a branch are fetched before the branch outcome is known IF ID ALU MEM WB IF ID ALU MEM WB BEQ R1,R2 next ADD R4, R1, R2 ADD R5, R2, R1 next : … What should happen If branch is not taken, next instruction in pipeline should be instruction at address PC+2 If branch is taken, next instruction in pipeline should be at address next What actually happens Instructions at PC+2 (IF & ID) and PC+4 (IF) are fetched before branch outcome is known (end of ALU) IF ID ALU MEM WB
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Lecture 24 Control Hazards beq $1,$2,X ??? sub $5,$2,$1
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This note was uploaded on 02/10/2010 for the course ECE 2300 at Cornell.

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Lecture24 - ENGRD 2300 Introduction to Digital Logic Design...

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