Lecture23

Lecture23 - ENGRD 2300 Introduction to Digital Logic Design...

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Lecture 23: 1 ENGRD 2300 Introduction to Digital Logic Design Pipelined Microprocessors Fall 2009
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Lecture 23: Announcements Lab 7 (last one!) on Blackboard Single cycle microprocessor Get an early start! Open labs Nov 23, and 24 Final labs Nov 30, Dec 1 and 2 Final report due Saturday, Dec 5 Lab partners? Final exam Tuesday Dec 15, 7:00pm Phillips Hall 101 2
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Lecture 23: 3 SRL R2,R2 BEQ R4,R0,8 ADD R3,R3,R1 SLL R1,R1 5: 6: 7: 8: 010 010 xxx x SRL 0 1 0 x x x x 100 x 1 SUB 0 0 0 0 010 1 011 011 001 0 SLL 0 1 0 x x x 001 001 xxx x ADD 0 1 0 x x x DR SA SB MB FS MD RW MW IMM BS OFF Single Cycle Microprocessor sext({OFF,0}) PC Adder +2 Decoder DR SA SB MB FS MD RW MW RF RW SA SB DR D_in ALU Data RAM DataA DataB V C Z N F m … F 0 SE IMM MB M_address Data_in MW MD 0 1 0 1 Inst. RAM MP 0 1 MP BS 0 1 Z Z’ N N’ C V 0 1 2 3 4 5 6 7
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Lecture 23: Stages of Instruction Execution Instruction Fetch (IF) Update PC; Increment PC; Fetch instruction Instruction Decode (ID) Decode instruction; Get register operands Execute (EX) Perform ALU operation Memory (MEM) Perform memory operation (optional) Write Back (WB) Store results of instruction into register Only one of these stages is active at a time! 4
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Lecture 23: 5 Single-cycle execution Increasing Instruction Parallelism IF/ ID/EX/MEM/WB Pipelined execution IF ID ALU MEM WB IF ID ALU MEM WB IF ID ALU MEM WB IF ID ALU MEM WB IF ID ALU MEM WB t=0 t=1 t=2 t=3 t=4 t=5 t=6 t=7 t=8 t=9 IF/ ID/EX/MEM/WB
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Lecture 23: 6 Pipelining Average cycles per instruction Latency : 5 cycles for every instruction Throughput : 1 instruction completed every cycle (ideal) Requirements Separate instruction and data memories Separate PC update adders Pipeline registers to hold info about each instruction in process More complex control 1 4 ns instructio for cycles of Number + = N N N N
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Lecture 23: 7 Pipelined Microprocessor (1) InstrFetch (IF) IF/ID.IR IM[PC] PC PC + 2 IF/ID.PC PC + 2 (2) InstrDecode (ID) ID/EX.AR REG[SA] ID/EX.BR REG[SB] ID/EX.DR DR ID/EX.IMM ext(IMM) ID/EX.JUMP IF/ID.PC + sext(IMM) M U X Control Signals RF SA SB DR D_in ALU V C Z N F m … F 0 I R A M RW M U X MD CU V C Z N OP P C PCL M U X PCJ MW D R A M D_IN +2 Adder IF/ID ID/EX EX/ME ME/WB MB Decoder EXT
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Lecture 23: 8 Pipelined Microprocessor M U X Control Signals RF SA SB DR D_in ALU V C Z N F m
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This note was uploaded on 02/10/2010 for the course ECE 2300 at Cornell.

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Lecture23 - ENGRD 2300 Introduction to Digital Logic Design...

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