Lecture22 - ENGRD 2300 Introduction to Digital Logic Design...

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Lecture 22: 1 ENGRD 2300 Introduction to Digital Logic Design Datapath and Control Single Cycle Microprocessor Fall 2009
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Lecture 22: 2 Announcements Lab 6 Make-up labs this week Prelim 2 TONIGHT in Phillips 101 Covers sequential logic Lectures through 17 Readings through Wakerly 8.5 Old prelims have been posted Lab 7 Has been posted Template files have been posted (with one test program) Open labs Nov 23, 24 Regular labs Nov 30, Dec 1, Dec 2 Lab reports due Dec 5 at 1:25pm NO POSTLAB Do you have/need/want a lab partner?
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Lecture 22: Readings Sections 7.1-7.8 Sections 5.1, 5.4, 7.13 Now’s the time to worry about the HDL (Verilog) stuff I.e., Review Verilog parts of Ch 6 Sections 8.1, 8.4 – 8.5 Sections 8.7 – 8.9 Sections 9.1 – 9.4 3
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Lecture 22: 4 Program Counter Replace hardwired control with a PC Register that points to the location in ROM of the next instruction (control word) Sequential instruction execution Instructions are executed in the order in which they are stored in ROM PC increases by 1 for each instruction executed Branch instruction execution Offset (positive or negative) is added to PC to calculate next address Condition codes used to decide to branch or not Program instructions still stored in ROM
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Lecture 22: 5 R2 <= R0 + R1 R1 <= M[R2] M[R2] <= R0 R3 <= R0 + 3 DR SA SB MB FS MD RW MW IMM 010 000 001 0 ADD 0 1 0 x 001 010 xxx 1 ADD 1 1 0 0 xxx 010 000 1 ADD x 0 1 0 011 000 xxx 1 ADD 0 1 0 3 Sequential Instruction Execution PC Adder 1 0: 1: 2: 3: ROM DR SA SB MB FS MD RW MW RF RW SA SB DR D_in ALU RAM DataA DataB V C Z N F m … F 0 SE IMM MB M_address Data_in MW MD 0 1 0 1
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