Lecture21 - ENGRD 2300 Introduction to Digital Logic Design...

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Lecture 21: 1 ENGRD 2300 Introduction to Digital Logic Design Datapath and Control Single Cycle Microprocessor Fall 2009
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Lecture 21: 2 Announcements Lab 6 If you cannot finish the lab this week, there will be a second chance next week. Also, make-up labs next week Prelim 2 Tues Nov 17, Make-up Thurs Nov 12, in 205 Thurston You must sign by TUESDAY to take Make-up Let me know if you want the early option on Nov 17 CS2110 prelim can be taken from 6:00pm to 7:30pm See ASAP me if any of this is a problem Covers sequential logic Lectures through 17 Readings through Wakerly 8.5 Old prelims have been posted Lab 7 Will be posted this week
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Lecture 21: Readings Sections 7.1-7.8 Sections 5.1, 5.4, 7.13 Now’s the time to worry about the HDL (Verilog) stuff I.e., Review Verilog parts of Ch 6 Sections 8.1, 8.4 – 8.5 Sections 8.7 – 8.9 Sections 9.1 – 9.4 3
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Lecture 21: 4 RF RW SA SB DR D_in ALU RAM DataA DataB V C Z N F m … F 0 SE IMM MB M_address Data_in MW MD 0 1 0 1 Programming the Basic Structure R2 <= R0 + R1 R1 <= M[R2] M[R2] <= R0 R3 <= R0 + 3 V C N Z CU DR SA SB MB FS MD RW MW DR SA SB MB FS MD RW MW IMM 010 000 001 0 ADD 0 1 0 x 001 010 xxx 1 ADD 1 1 0 0 xxx 010 000 1 ADD x 0 1 0 011 000 xxx 1 ADD 0 1 0 3
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Lecture 21: 5 Simple Multiplication Algorithm Multiply A 2 A 1 A 0 by B 2 B 1 B 0 A 2 A 1 A 0 B 2 B 1 B 0 (A 2 A 1 A 0 ) ° B 0 (A 2 A 1 A 0 ) ° B 1 (A 2 A 1 A 0 ) ° B 2 P 4 P 3 P 2 P 1 P 0 Implement as sequence of shifts and adds R1 contains A Shift left each iteration R2 contains B Check if LSB = 1 and shift
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Lecture21 - ENGRD 2300 Introduction to Digital Logic Design...

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