Lecture18 - ENGRD 2300 Introduction to Digital Logic Design...

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Lecture 18: 1 ENGRD 2300 Introduction to Digital Logic Design Clocking Long and Short Paths Asynchronous Inputs MTBF Fall 2009 Lecture 18 Lecturer: Dr. Wesley E. Swartz November 3, 2009
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Lecture 18: 2 Announcements HW4 Has been posted on Blackboard Due Friday, Nov 6 at 1:25pm Lab 6 Has been posted on Blackboard Prelab due Sunday, Nov 8 (but you will not get early feedback) Labs meet Nov 9,10, 11 Prelim 1 Scores have been posted on Blackboard Prof. Long will return them Thursday Makeup Lab If you have missed a lab due to illness, this afternoon is your chance to make it up! Student Written Exam Questions Please hand in now…
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Lecture 18: Readings Sections 7.1-7.8 Sections 5.1, 5.4, 7.13 Now’s the time to worry about the HDL (Verilog) stuff I.e., Review Verilog parts of Ch 6 Sections 8.1, 8.4 – 8.5 (Today) Sections 8.7 – 8.9 (Today) Sections 9.1-9.4 (Thursday) 3
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Lecture 18: 4 MSI Shift Registers
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Lecture 18: 5 Ring Counter “Shift-register counter” Single “1” shifts through the state bits
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Lecture 18: 6 4-bit Ring Counter Load 0001 when RESET asserted Shift left otherwise and wraparound 0001 0010 0100 1000 0001 Wraparound: Tie QA to LIN
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Lecture 18: 7 Not Self-Correcting! Get into an invalid state Æ cycle through an invalid sequence forever!
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Lecture 18: 8 Self-Correcting 4-bit Ring Counter Force all invalid states to lead to the valid sequence Æ Shift left a 1 into LIN only if three LSBs are all 0
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Lecture 18: 9 Self-Correcting 4-bit Ring Counter
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Lecture 18:10 Sequential Design Methodology Reliable sequential design requires Properly handling the clock signal Managing clock skew
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This note was uploaded on 02/10/2010 for the course ECE 2300 at Cornell University (Engineering School).

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Lecture18 - ENGRD 2300 Introduction to Digital Logic Design...

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