Lecture17

Lecture17 - ENGRD 2300 Introduction to Digital Logic Design...

Info iconThis preview shows pages 1–8. Sign up to view the full content.

View Full Document Right Arrow Icon
ENGRD 2300 Introduction to Digital Logic Design Fall 2009 Registers Counters Shift Registers Lecture 17: 1
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Announcements HW4 Will be posted on Blackboard soon ill be due Friday, Nov 6 Will be due Friday, Nov 6 Lab 6 Will be posted on Blackboard soon Prelab due Sunday, Nov 8 (but you will not get early feedback) Labs meet Nov 9,10, 11 Lab 7 Postlab instead of prelab. pen labs Nov 23, 24, Regular labs Dec 1,2,3 Open labs Nov 23, 24, Regular labs Dec 1,2,3 Lecture 17: 2
Background image of page 2
Readings Sections 7.1-7.8 Sections 5.1, 5.4, 7.13 Now’s the time to worry about the HDL (Verilog) stuff I.e., Review Verilog parts of Ch 6 Sections 8.1, 8.4 – 8.5 (Today) Sections 8.7 – 8.9 (Thursday) Lecture 17: 3
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Assignment Create 1 exam question on a topic to be covered on Prelim 2 State your question as clearly and unambiguously as you can olve your exam question Solve your exam question Tell me how much time you think your problem should take to solve Tell me how many points (out of 100) your question should be worth Due Tuesday at start of class Lecture 17: Good questions may be used in Prelim 2! 4
Background image of page 4
Finite String Pattern Recognizer (Step 2, cont’d) S0 [0] reset (Step , co t d) Reuse states as much as possible ...1 ...0 1 0 S4 [0] S1 [0] 1 0 Look for same meaning State minimization wer state bits S2 1 S5 0 1 1 Æ fewer state bits nce all states have a 1 ...01 [0] 0 [0] 0 ...10 Once all states have a complete set of ansitions, we have a ...010 ...100 0 or 1 S3 [1] S6 [0] transitions, we have a final state diagram Lecture 17: 5
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Remember our State Machines? utput Output Output Output ombinational Output Signals Combinational Logic Network Signals ext State Combinational Logic Network Input Signals Next State Combinational Logic Network Input Signals Next State Combinational Logic Network Next State Current State FF Next State Current State FF Signals Signals FF Signals Signals FF Lecture 17: 6
Background image of page 6
Remember our Coding Rules? (L11) Always use blocking assignments in always blocks intended to create combinational logic Always use nonblocking assignments in lways blocks tended to create equential always blocks
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 8
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 02/10/2010 for the course ECE 2300 at Cornell.

Page1 / 36

Lecture17 - ENGRD 2300 Introduction to Digital Logic Design...

This preview shows document pages 1 - 8. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online