Lecture16 - ENGRD 2300 Introduction to Digital Logic Design Fall 2009 Verilog Lecture 16 1 Announcements Prelim 1 Being graded Regrade Procedure

Info iconThis preview shows pages 1–11. Sign up to view the full content.

View Full Document Right Arrow Icon
ENGRD 2300 Introduction to Digital Logic Design Fall 2009 Verilog Lecture 16: 1
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Announcements Prelim 1 Being graded. .. egrade Procedure Regrade Procedure Fill out the regrade request form within one week HW4 to be posted soon Lecture 16: 2
Background image of page 2
Readings Sections 7.1-7.8 Sections 5.1, 5.4, 7.13 (Today) Now’s the time to worry about the HDL (Verilog) stuff I.e., Review Verilog parts of Ch 6 Sections 8.1, 8.4 – 8.5 (Thursday) Lecture 16: 3
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Hardware Description Languages Why use an HDL? Describe complex designs (millions of gates) put to synthesis tools (synthesizable subset) Input to synthesis tools (synthesizable subset) Design exploration with simulation hy not use a general purpose language? Why not use a general purpose language? Support for structure and instantiation Support for describing bit-level behavior upport for timing Support for timing Support for concurrency Verilog vs. VHDL (VHSIC HDL) Verilog is relatively simple and close to C VHDL is close to Ada (DoD-sponsored language) erilog has 50% of the world digital design market Lecture 16: 4 Verilog has 50% of the world digital design market (larger share in US)
Background image of page 4
Not a Programming Language With every keystroke say, “I’m designing hardware” Concurrent language <= ~b; a <= b; c <= d; Which happens first? Warnings It’s easy to create tons of hardware It’s easy to create descriptions that can’t be ynthesized Lecture 16: 5 synthesized
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
HDL-based design flow Back-end differs by target technology May be PLD, CPLD, FPGA, or ASIC For ASICs, verification and fitting phases are usually much Lecture 16: 6 longer (as a fraction of overall project time)
Background image of page 6
Verilog Developed in the early 1980s by Gateway Design Automation (later bought by Cadence) Syntactically similar to C Shares market 50/50 with VHDL sed for design description simulation and Used for design description, simulation, and synthesis ynthesis became practical in the early 90s and use Synthesis became practical in the early 90s and use of VHDL and Verilog has taken off since then Note that only a subset of the language can be synthesized Easy to code something that can’t be synthesized Lecture 16: 7 Try to distinguish, which is which!
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Verilog Program Structure System is a collection of modules Module corresponds to a single piece of hardware Declarations Describe names and types of inputs and outputs Describe local signals, variables, constants, etc. Statements specify what the module does odule declarations module statements Lecture 16: 8
Background image of page 8
Verilog declarations module A Hierarchy statements module B module C module D declarations statements declarations statements declarations statements declarations declarations module E module F Lecture 16: 9 statements statements
Background image of page 9

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Verilog Program Structure module V2to4dec( i0,i1,en,y0,y1,y2,y3 ); input i0,i1,en; utput y0,y1,y2,y3; eclarations output y0,y1,y2,y3; wire noti0,noti1; t U1( ti0 i0) Declarations not U1(noti0,i0); not U2(noti1,i1);
Background image of page 10
Image of page 11
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 02/10/2010 for the course ECE 2300 at Cornell University (Engineering School).

Page1 / 34

Lecture16 - ENGRD 2300 Introduction to Digital Logic Design Fall 2009 Verilog Lecture 16 1 Announcements Prelim 1 Being graded Regrade Procedure

This preview shows document pages 1 - 11. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online