Lecture15 - ENGRD 2300 Introduction to Digital Logic Design...

Info iconThis preview shows pages 1–14. Sign up to view the full content.

View Full Document Right Arrow Icon
ENGRD 2300 Introduction to Digital Logic Design Fall 2009 Sequential Circuit Design Sequential Circuit Synthesis Lecture 15: 1
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Announcements Prelim 1 Being graded. .. ab 5 has been posted Lab 5 has been posted Prelab 5 due Monday Oct 23 Regrade Procedure Fill out the regrade request form within one week HW4 to be posted soon Lecture 15: 2
Background image of page 2
Readings Chapter 1 Sections 3.1-3.3 Sections 2.1–2.9 Section 4.1 – 4.4 Sections 6.1 – 6.11 Sections 7.1-7.8 Sections 5.1, 5.4, 7.13 (Tuesday) Now’s the time to worry about the HDL (Verilog) stuff I.e., Review Verilog parts of Ch 6 Lecture 15: 3
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Exercises Create a circuit that creates a 1 clock cycle pulse when a button is pressed. State machine State/output table tate variable assignment State variable assignment Transition/output table Modify this design to output a 5 μ s pulse Assume a 1MHz clock Lecture 15: 4
Background image of page 4
Moore Solution X’ X Z=0 Z=1 X’ 1 Z=0 X CLK X Z Lecture 15: 5
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Mealy Solution ’/0 X/0 W0 W1 X’/1 X/0 X/0 CLK X Z CLK X Lecture 15: 6 Z
Background image of page 6
Moore Solution X’ 1 X X’ =0 1 111 Z=0 Z=0 Z=1 Z=1 Z=1 Z=1 Z=1 X Lecture 15: 7
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Synthesis Using J-K Flip-Flops Transformation from Transition to Excitation Tables requires different techniques haracteristic Equation: Q*= J·Q’+K’·Q Characteristic Equation: Q JQ + KQ Must use Application Table for J-K flip-flops For each combination of Q and Q*, tells you values for J and K inputs QQ * JK 000 d 0 1 1 d 10d 1 11d 0 Lecture 15: 8
Background image of page 8
J-K FF Excitation/Output Table se Application table to produce JK value pairs Use Application table to produce JK value pairs EN UP Q1 Q0 00 01 11 10 Z1 Z0 00 00 00 01 10 00 01 01 01 10 00 01 1 0 0 0 1 1 10 10 10 01 10 10 10 00 01 10 Q1* Q0* EN UP Q1 Q0 00 01 10 Z1 Z0 00 0d,0d 0d,0d 0d,1d 1d,0d 00 01 0d,d0 0d,d0 1d,d1 0d,d1 01 d0,d1 d0,d1 d0,d1 d1,d0 Lecture 15: 9 10 d0,0d d0,0d d1,0d d1,1d 10 J1 K1,J0 K0
Background image of page 9

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
J-K FF Karnaugh Maps J1 = EN·UP’·Q0’ + EN·UP·Q0 00 01 11 10 00 0001 00 01 11 10 00 dddd J1 K1 EN EN K1 = EN·UP’ + EN·Q0’ 01 0010 11 01 11 Q1 Q0 Q1 Q0 J0 = EN·UP’·Q1 + EN EN 10 10 0011 0 0 UP UP EN·UP·Q1’ 0 = EN’·Q1 + 00 01 11 10 00 01 J0 K0 00 01 11 10 00 01 K0 = EN ·Q1 + EN·UP + EN· Q1’ Q1 Q0 Q1 Q0 11 1110 10 11 10 Lecture 15:10 UP UP
Background image of page 10
Modulo-3 Counter Lecture 15:11
Background image of page 11

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Sequential Logic Design Digital designs are partitioned into datapath and control Finite State Machines (FSMs) are the decision- making control logic of digital designs Four step FSM design process Implementation examples Finite string pattern recognizer Lecture 15:12 Traffic light controller
Background image of page 12
Datapath and Control Digital hardware systems = datapath + control Datapath: registers, memories, arithmetic units (e.g.,
Background image of page 13

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 14
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 02/10/2010 for the course ECE 2300 at Cornell University (Engineering School).

Page1 / 37

Lecture15 - ENGRD 2300 Introduction to Digital Logic Design...

This preview shows document pages 1 - 14. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online