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Lecture15 - ENGRD 2300 Introduction to Digital Logic Design...

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ENGRD 2300 Introduction to Digital Logic Design Fall 2009 Sequential Circuit Design Sequential Circuit Synthesis Lecture 15: 1
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Announcements Prelim 1 Being graded... Lab 5 has been posted Prelab 5 due Monday Oct 23 Regrade Procedure Fill out the regrade request form within one week HW4 to be posted soon Lecture 15: 2
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Readings Chapter 1 Sections 3.1-3.3 Sections 2.1–2.9 Section 4.1 – 4.4 Sections 6.1 – 6.11 Sections 7.1-7.8 Sections 5.1, 5.4, 7.13 (Tuesday) Now’s the time to worry about the HDL (Verilog) stuff I.e., Review Verilog parts of Ch 6 Lecture 15: 3
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Exercises Create a circuit that creates a 1 clock cycle pulse when a button is pressed. State machine State/output table State variable assignment Transition/output table Modify this design to output a 5 μ s pulse Assume a 1MHz clock Lecture 15: 4
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Moore Solution X’ X’ 1 X Z=0 Z=1 Z=0 X CLK X Z Lecture 15: 5
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