lecture1_ee689_intro

lecture1_ee689_intro - ECEN689: Special Topics in...

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Sam Palermo ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2010 Lecture 1: Introduction
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Class Topics System and design issues relevant to high-speed electrical (and optical) signaling Channel properties Modeling, measurements, communication techniques High-Speed link circuits Drivers, receivers, equalizers, timing systems Link system design Modeling and performance metrics Link system examples 2
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Administrative Instructor: Sam Palermo 315E WERC Bldg., 845-4114, [email protected] Office hours: MW 10:30am-12pm Lectures: MWF 9:10am-10am, ZACH 223C Class web page http://www.ece.tamu.edu/~spalermo/ecen689.html 3
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Class Material Textbook: Digital Systems Engineering, W. Dally and J. Poulton, Cambridge University Press, 1998. References High-Speed Digital Design: A Handbook of Black Magic, H. Design of Integrated Circuits for Optical Communications, B. Razavi, McGraw-Hill, 2003. Technical Papers Class notes Posted on the web at least 1 hour before lecture Will hand out limited number of hard copies in class 4
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Grading Exams (50%) Two midterm exams (25% each) Homework (20%) Collaboration is allowed, but independent simulations and write-ups Need to setup CADENCE simulation environment Due at beginning of class No late homework will be graded Final Project (30%) Groups of 1-2 students Report and PowerPoint presentation required 5
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Prerequisites This is a circuits AND systems class Circuits ECEN474 or approval of instructor Basic knowledge of CMOS gates, flops, etc… Circuit simulation experience (HSPICE, Spectre) Systems Basic knowledge of s- and z-transforms Basic digital communication knowledge MATLAB experience 6
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Simulation Tools Matlab Stateye (Statistical BER link analysis) Cadence 90nm CMOS device models Can use other technology models if they are a 90nm or more advanced CMOS node Other tools, schematic, layout, etc… are optional 7
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Reading HW1 papers Chapter 1: Introduction Material Chapter 3.1 – 3.4: Wire Models 8
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Desktop Computer I/O Architecture Many high-speed I/O interfaces Key bandwidth bottleneck points are memory (FSB) and graphics interfaces (PCIe) Near-term architectures ̶ Integrated memory controller with serial I/O (>5Gb/s) to memory ̶ Increasing PCIe from 2.5Gb/s (Gen1) to 8Gb/s (Gen3) Other serial I/O systems ̶ Multi-processor systems ̶ Routers 9
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This note was uploaded on 02/14/2010 for the course ECEN 689 taught by Professor Enjeti during the Spring '07 term at Texas A&M.

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lecture1_ee689_intro - ECEN689: Special Topics in...

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