hw1 - Low-Power Source-Synchronous Link 4. G. Balamurugan...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
January 20, 2010 ECEN 689: High-Speed Links Homework #1 Due: 1-29-2010, 9:00AM Homeworks will not be received after due. Instructor: Sam Palermo Read the following high-speed link overview material and recent design papers which are posted on the website. Link Overview Material 1. S. Palermo, “High-speed electrical links,” PhD Thesis , Ch. 2.1, Stanford University, Sept. 2007. 2. M. Horowitz et al ., “High-speed electrical signaling: overview and limitations,” IEEE Micro , vol. 18, no. 1, Jan.Feb. 1998, pp. 12-24. Recent Design Papers State-Of-The-Art Backplane Link (Non-ADC-based) 3. J. Bulzacchelli et al ., “A 10Gb/s 5tap DFE/4tap FFE transceiver in 90nm CMOS technology,” IEEE J. Solid-State Circuits , vol. 41, no. 12, Dec. 2006, pp. 2885-2900.
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: Low-Power Source-Synchronous Link 4. G. Balamurugan et al ., A scalable 5-15Gbps, 14-75mW low-power I/O transceiver in 65nm CMOS, IEEE J. Solid-State Circuits , vol. 43, no. 4, Apr. 2008, pp. 1010-1019. ADC-Based Backplane Link 5. M. Harwood et al ., A 12.5Gb/s serdes in 65nm CMOS using a baud-rate ADC with digital receiver equalization and clock recovery, IEEE International Solid-State Circuits Conference , Feb. 2007. Optical Interconnect Link 6. S. Palermo et al ., A 90nm CMOS 16Gb/s transceiver for optical interconnects, IEEE J. Solid-State Circuits , vol. 43, no. 5, May 2008, pp. 1235-1246. Write a one-page summary report on one of the above recent design papers (3-6)....
View Full Document

Ask a homework question - tutors are online