L4 Pipelining - Computer Science 230H Pipelining Prepared...

Info iconThis preview shows pages 1–9. Sign up to view the full content.

View Full Document Right Arrow Icon
Computer Science 230H Pipelining Prepared by Michael Jack - Fall 2007
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Pipelining 2 References The information and figures for the following slides were prepared from the following source: Patterson, D., and Hennessy J., Computer Organization and Design, 3rd edition, 2005 Stallings, W., Computer Organization and Architecture: Designing for Performance 7 th edition, 2006 Hircock B., Computer Science 230 Course Notes
Background image of page 2
Pipelining 3 Objectives Describe processor organization. Describe register organization. Analyze instruction cycle. Introduce instruction pipelining. Discuss pipelining strategies and limitations.
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Pipelining 4 Introduction A processor includes both user-visible registers and control/status registers. – User register may be GPRs or have a special use. – Control and status registers are used to control the operation of the processor. Processors make use of instruction pipelining to speed up execution. – Pipelining involves breaking up the instruction cycle into a number of separate stages that occur in sequence • Fetch instruction, decode instruction, determine operand addresses, fetch operands, execute instruction, and write operand result. – The occurrence of branches and dependencies between instructions complicates the design and use of pipelines.
Background image of page 4
Pipelining 5 Processor Organization Every processor is required to do be able to do the following: – Fetch instruction – read it from memory (register, cache, main memory.) – Interpret instruction – decode it to determine what action is required. – Fetch data – (if requested) read data from memory or an I/O module. – Process data – (if requested) perform an arithmetic or logical operation on data. – Write data - (if requested) write data to memory or an I/O module. To accomplish all of the above processors needs a small internal memory.
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Pipelining 6 Processor Organization (cont) The ALU does the actual computation or processing of data. The CU controls the movement of data and instructions. Registers are the minimal temporary internal storage.
Background image of page 6
Pipelining 7 Processor Organization (cont) ALU operates only on data in the internal processor memory. Internal CPU bus transfers data between the various registers and the ALU.
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
8 Register Organization Registers form the highest level of the memory hierarchy – Small set of high speed storage locations. – Temporary storage for data and control information. Two types of registers – User-visible • May be referenced by assembly-level instructions and are thus “visible” to the user. – Control and status registers • Used to control the operation of the CPU. • Most are not visible to the user.
Background image of page 8
Image of page 9
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 46

L4 Pipelining - Computer Science 230H Pipelining Prepared...

This preview shows document pages 1 - 9. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online