Architectures part 1

Architectures part 1 - High Performance Computing COIS...

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Architectures: Part 1 (SISD, SIMD, MISD) High Performance Computing COIS 4350H Winter 2010 Outline for today’s lecture • Moore’s law • Flynn’s taxonomy • Vector Processors • Processor Arrays • Systolic Arrays HPC architectures • maximize: – performance – price/performance • to achieve maximization: – reduce time per instruction – increase the number of useful instructions per clock cycle • using single processor • using multiple processors Moore’s Law http://en.wikipedia.org/wiki/Moore's_law
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Hardware Development Power wall + ILP wall + memory wall Uniprocessor performance doubles every 18 months Law of diminishing returns on more HW for ILP, focus on thread and data-parallel approaches Instruction level parallelism is sufficient, comes free Memory wall Mulitplies slow, adds fast, memory accesses free We hit a “Power wall” Power is free, Transistors expensive. new old Flynn’s Taxonomy – Version I Single Data Stream Multiple Data Stream Single instruction SISD Uniprocessors SIMD Vector Processors, Processor Arrays Multiple instructions MISD Systolic Arrays MIMD Multiprocessors Multicomputers SISD (single processor, single instruction stream) • operating sequentially on a single data stream • these are the traditional single-processor sequential computers • also known as von Neumann architecture • mainframes, workstations, PCs Flynn’s Taxonomy – Version I Single Data Stream Multiple Data Stream Single instruction SISD Uniprocessors SIMD Vector Processors, Processor Arrays Multiple instructions MISD Systolic Arrays MIMD Multiprocessors Multicomputers
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SIMD (Single instruction, multiple data) • single instruction stream is broadcast to every processor • vector computers: – instruction set includes operations on vectors as well as scalars • Two architectures fit this category – Pipelined vector processor : • streams data through pipelined arithmetic units • example: Cray-I
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Architectures part 1 - High Performance Computing COIS...

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