Architectures part 2

Architectures part 2 - High Performance Computing COIS...

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Architectures: Part 2 (MIMD) High Performance Computing COIS 4350H Winter 2010 Outline for today’s lecture • MIMD architectures • extension of Flynn’s taxonomy • Multiprocessors • centralized • distributed • Cache coherency • Multicomputers • symmetrical • asymmetrical • Clusters Flynn’s Taxonomy – Version I Single Data Stream Multiple Data Stream Single instruction SISD Uniprocessors SIMD Vector Processors, Processor Arrays Multiple instructions MISD Systolic Arrays MIMD Multiprocessors Multicomputers MIMD (multiple instruction, multiple data) • each processor can independently execute its own instruction stream on its own data stream • asynchronous, with more coarse-grained parallelism • run a smaller number of parallel processes – one for each processor, operating on the large chunks of data local to each processor
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Parallel Organizations - MIMD Shared Memory Parallel Organizations – MIMD Distributed Memory Flynn’s Taxonomy – Version II MIMD ( multiple instructions, multiple data) • Multiprocessors • centralized • distributed • Multicomputers • symmetrical • asymmetrical
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Centralized Multiprocessors • extension of uniprocessor • Bus connects to additional CPUs • all processors share same memory • often called UMA (Uniform memory access) multiprocessor or SMP (symmetric multiprocessor) • Memory access time same for all CPUs • limited scalability Centralized Multiprocessor Centralized Multiprocessors (continued) • uses shared and private data values – private data: items used only by a single processor – shared data: values used by multiple processors • communication through shared values (for example pointers) • two main problems: – cache coherency – synchronization Problems Associated with Shared Data • Cache coherence – Replicating data across multiple caches reduces contention – How to ensure different processors have same value for same address? • Synchronization – Mutual exclusion – Barrier
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Cache-coherence Problem Cache CPU A Cache CPU B Memory 7 X Cache-coherence Problem CPU A CPU B Memory 7 X 7 Cache-coherence Problem CPU A CPU B Memory 7 X 7 7 Cache-coherence Problem CPU A CPU B Memory 2 X 7 2
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Write Invalidate Protocol CPU A CPU B 7 X 7 7 Cache control monitor Write Invalidate Protocol CPU A CPU B 7 X 7 7 Intent to write X Write Invalidate Protocol CPU A CPU B 7 X 7 Intent to write X Write Invalidate Protocol CPU A CPU B X 2 2
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Cache Coherency for Centralized Multiprocessors • Shared data may be replicated across caches • reading of values is no problem • if writes are allowed, we must ensure that different processors do not have different values for the same variable
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Architectures part 2 - High Performance Computing COIS...

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