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Unformatted text preview: Lecture 3: Lecture Boolean Logic Binary Logic/Boolean Algebra
Deals with variables that take on two discrete values (0,1) Deals Describes in a mathematical way, manipulation and Describes processing of binary data Variables represented via letters Variables 3 basic logical ops: basic
– AND (represented by •, e.g. A • B) – OR (represented by +, e.g. A + B – NOT (represented via ’ or , e.g. A’, A adapted from Patterson 00 ©UCB, and Ballesteros ‘01 Truth Tables: How many entries for N inputs?
X • Y: Any boolean function can be represented this way Any adapted from Patterson 00 ©UCB, and Ballesteros ‘01 Boolean Algebra and Logic Gates
Circuits calculate binary functions Circuits
voltage source => ~ A B L <= light source – light is on when both switches are closed: L=A•B adapted from Patterson 00 ©UCB, and Ballesteros ‘01 Combinational Logic
Digital signals Digital – high voltage, “on”, “true”, 1, or “asserted”
– low voltage, “off”, “false”, 0, or “deasserted” Two types logic blocks Two
– combinational (no memory) – sequential (have state or memory) Output completely determined by input Output Truth table ≡ equation ≡ circuit Truth
– transformation purely mechanistic
adapted from Patterson 00 ©UCB, and Ballesteros ‘01 Standard Form
Term contains one representation of each variable Term Sum of Products: Sum
– Boolean expression consisting of AND terms, of 1 or more literals each where terms are ORed:
F(x,y,z) = x + x’yz F(x,y,z
Standard term Product of Sums: Product
– Boolean expression consisting of OR terms, of 1 or more literals each where terms are ANDed:
F(x,y,z) = x(yz)(x’y’z) F(x,y,z
Standard term
adapted from Patterson 00 ©UCB, and Ballesteros ‘01 Minterms and Maxterms
Minterms: each of the combinations of inputs Minterms given n variables and the AND operator
– var is primed if value is 0 Maxterms: each of the combinations of inputs Maxterms given n vars and the OR operator
– var is primed if value is 1 (simplifies conversions)
A 0 0 1 1 B 0 1 0 1 minterm A’B’ A ’B AB’ AB maxterm A+B A+B’ A’+B A’+B’
adapted from Patterson 00 ©UCB, and Ballesteros ‘01 Canonical Form
∞ number of expressions specify same function Canonical form is unique Canonical
– Composed of standard terms – sum of minterms (ORing of minterms)
e.g. F(x,y,z) = x’yz + xyz’ e.g. – product of maxterms (ANDing of maxterms)
e.g. F(a,b) = (a+b)(a’+b’) e.g. Any boolean function can be expressed in this way Any
adapted from Patterson 00 ©UCB, and Ballesteros ‘01 Expressing Boolean Functions
Given the truth table for a function, F, generate the Given function as sum of minterms:
1. 2.
m0 m1 ... generate all minterms for which F = 1 take the OR of all terms from (1) m7 f1 = x’y’z + xy’z’ + xyz = ∑m(1,4,7) f2 = adapted from Patterson 00 ©UCB, and Ballesteros ‘01 Canonical Forms
Sum of minterms Sum
– ORing of minterms for which F = 1
Recall: 0 vals are primed and 1s are not Recall: Product of maxterms Product
– ANDing of maxterms for which F = 0
Recall: 1 vals are primed and 0s are not Recall: Complement Complement
– ORing of minterms for which F = 0 – ANDing of maxterms for which F = 1
adapted from Patterson 00 ©UCB, and Ballesteros ‘01 Generating Canonical SOP Form
Expand expression to sum of AND terms via Expand distributive property Check that each term contains all variables Check
– If a term is missing a var
1. 2. AND with (x+x’), where x is the missing var Repeat this for each missing var, in each term A= A(B+B’)(C+C’) = (AB+AB’)(C+C’) =ABC+ABC’+AB’C+AB’C’ F = A + B’C
B’C = B’C(A+A’) = AB’C+A’B’C F = ABC+ABC’+AB’C+AB’C’+ AB’C+A’B’C = ABC+ABC’+AB’C+AB’C’+A’B’C
adapted from Patterson 00 ©UCB, and Ballesteros ‘01 Canonical Form to Truth Table
F(A,B,C) = ABC + ABC’+ AB’C + AB’C’+ A’B’C = ∑m(1,4,5,6,7)
A B C F adapted from Patterson 00 ©UCB, and Ballesteros ‘01 Truth Tables
Assume 3 inputs (A,B,C) and 3 outputs (D,E,F) Assume
– D = 1 if at least one input = 1, E = 1 if exactly two inputs = 1, F = 1 when all inputs = 1 A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1
adapted from Patterson 00 ©UCB, and Ballesteros ‘01 D E F A B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 D 0 1 1 1 1 1 1 1 E 0 0 0 1 0 1 1 0 F 0 0 0 0 0 0 0 1 Boolean Algebra
D = 1 if at least one input = 1 if F = 1 when all inputs = 1 when E = 1 if exactly two inputs = 1 if 0 0 0 0 1 1 1 1 What are the equations for the above problem? What adapted from Patterson 00 ©UCB, and Ballesteros ‘01 Boolean Simplification
Complexity of logic gates implementing F is directly Complexity related to complexity of the Boolean expression
– so, simplify! Karnaugh maps Karnaugh
– map of squares
each square represents one minterm each – visual diagram of all ways F may be expressed in canonical form – straightforward procedure for minimization
adapted from Patterson 00 ©UCB, and Ballesteros ‘01 Karnaugh Maps
mark squares whose minterms belong to F mark
e.g. x+y = x(y+y’)+y(x+x’) = xy+xy’+xy+x’y = xy + xy’ + x’y = m1 + m2 + m3 y x 0 x 1 0 y 1 1 1 1 m0 m2 m1 m3 adapted from Patterson 00 ©UCB, and Ballesteros ‘01 3 and 4 Variable KMaps
y x
x yz 00 01 11 10 Note that adjacent squares are numbered in such a way as to differ in only 1 bit value
y 0 1 x’y’z x’y’z x’yz x’yz’ ’ xy’z’ xy’z xyz xyz’ w yz 00 01 11 10 wx 00 w’x’y’ w’x’y’ w’x’yz w’x’yz z’ z ’ 01 w’xy’z w’xy’z w’xyz w’xyz’ 11 ’ 10 wxy’z’ wxy’z wxyz wxyz’ z wx’y’z wx’y’z wx’yz wx’yz’ ’ x adapted from Patterson 00 ©UCB, and Ballesteros ‘01 KMaps
Any 2 adj squares differ by only 1 var, primed in Any one and unprimed in the other
– sum of their minterms can be simplified to single AND term of 1 fewer literal – consider m5 + m7 = xy’z + xyz = xz(y+y’) = xz
y x yz 00 01 11 10 x x’y’z x’y’z x’yz x’yz’ 0 ’ 1 xy’z’ xy’z xyz xyz’
z
adapted from Patterson 00 ©UCB, and Ballesteros ‘01 Kmap simplification
Group squares in blocks of 2 (2, 4, 8, etc) Group
– 2 squares eliminates 1 var – 4 squares eliminates 2 vars … Always begin with blocks for which there are Always fewest adjacent squares Group as many squares together as possible Group Make as few blocks as possible cover all squares Make of the function
adapted from Patterson 00 ©UCB, and Ballesteros ‘01 Kmap simplification
1. 2. 3. Group squares in blocks of 2 (2, 4, 8, etc), beginning w/ blocks for which there are fewest adjacent squares Group as many squares together as possible Make as few blocks as possible cover all squares of the function
c ab 00 01
a cd 00 12 01 13 11 14
d 11 12 10 b 11 10 10 12 12 what is the simplified form? adapted from Patterson 00 ©UCB, and Ballesteros ‘01 Gates Implement Logic Functions
AND OR NOT All logic functions can be built with these. adapted from Patterson 00 ©UCB, and Ballesteros ‘01 Combinational Logic
Decoders: important basic building block, primarily Decoders: used for addressing
– n inputs (interpreted as addr), 2n possible outputs Encoders: to generate the address of an active input Encoders: line
– 2n inputs, nbit output inputs, Multiplexors (MUX’s): used extensively n data inputs plus ceiling (log2 n) ⎡log 2 n ⎤ selector inputs
adapted from Patterson 00 ©UCB, and Ballesteros ‘01 Combinational Circuits: Decoder Decoder
ninputs, 2n outputs
– can consider to be a minterm generator – only one output is 1 at any given z time primarily for addressing: nprimarily bit input interpreted as an address x route data from common route source to one of several dest. (demultiplexor)
y adapted from Patterson 00 ©UCB, and Ballesteros ‘01 Combinational Circuits: Encoder
2k inputs and k outputs opposite of decoder: opposite generates address of input line adapted from Patterson 00 ©UCB, and Ballesteros ‘01 Combinational Circuits: Multiplexor (mux)
ninputs, select signal (control) aka data selector since output is one of the inputs aka selected by control
– can have arbitrary number of inputs (n inputs requires ceiling(log2 n) selector inputs) – used to route data from one of several sources to common destination S
A B 0 1 C adapted from Patterson 00 ©UCB, and Ballesteros ‘01 Combinational Logic
Sumofproducts form Sum
– i.e. ((A•B)+(B•C)+(A•C)) – From truth table entries resulting in true output – corresponds to programmable logic array (PLA) PLA: two level circuit PLA:
– stage1: AND gate array (inputs) – stage2: OR gate array (outputs) adapted from Patterson 00 ©UCB, and Ballesteros ‘01 Combinational Circuits:PLA (programmable logic array)
generalpurpose logic general element capable of implementing any Boolean function
– directly implement truth table for set of functions x y z x twolevel circuit two corresponding to SOP form
– stage 1: array of AND gates – stage 2: array of OR gates A A B B C C adapted from Patterson 00 ©UCB, and Ballesteros ‘01 What is the SOP form for this table?
inputs A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 D 0 1 1 1 1 1 1 1 outputs E 0 0 0 1 0 1 1 0 F 0 0 0 0 0 0 0 1 adapted from Patterson 00 ©UCB, and Ballesteros ‘01 How would we implement this table as a PLA?
3 inputs
A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 D 0 1 1 1 1 1 1 1 3 outputs
E 0 0 0 1 0 1 1 0 F 0 0 0 0 0 0 0 1 How many inputs (AND gates)? How many outputs (OR gates)?
adapted from Patterson 00 ©UCB, and Ballesteros ‘01 ...
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This note was uploaded on 02/15/2010 for the course CS 324 taught by Professor Lballesteros during the Fall '08 term at Mt. Holyoke.
 Fall '08
 LBallesteros
 Computer Architecture

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