Unformatted text preview: CS324: Computer CS324: Architecture
Combinational Logic and Simple Arithmetic Logic Circuits Logic
– Comprise CPU – 1 and only 1 output for each possible input combination only – e.g. Decoder, encoder, mux Sequential Sequential
– Memory elements – Output dependent upon input and current state and Logic Design Logic
CarryIn Operation Similarity b/w digital and software Similarity design
– Components put together to make “black boxes” with specified interface
e.g. Input and output e.g. a0 b0 CarryIn ALU0 CarryOut Result0 a1 b1 CarryIn ALU1 CarryOut Result1 – Join “black boxes” to form larger “black boxes” a2 b2 CarryIn ALU2 CarryOut Result2 Focus on what Focus what procedure/program/circuit does, before addressing how how
a31 b31 CarryIn ALU31 Result31 Combinational Circuits: PLA Combinational
x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 A 0 1 1 1 1 1 1 1 B 0 0 0 1 0 1 1 0 C 0 0 0 0 0 0 0 1
x x y z x A B C A=x+y+z B = (xyz’)+(xy’z)+(x’yz) C = xyz Combinational Circuits Combinational
Can implement 1-bit adder Can
– For what values of x, y does the sum, x+y = 1? sum – For what values of x,y do we generate a carry? x
This information can be used to derive the boolean functions whose implementation generates an adder. y 0 1 0 1 S C 0 0 1 1 Combinational Circuits Combinational
implement 1-bit adder implement
– For what values of x, y is the sum 1?
derives the boolean derives function for addition x 0 0 1 1 y 0 1 0 1 S 0 1 1 0 C 0 0 0 1 – For what values of x,y do we generate a carry?
derives the boolean derives function for the carry Do you see any limitations to a 1-bit adder? Combinational Circuits Combinational
Previous was ½-adder (adds Previous only 2 bits) Full-adder adds 2 significant Full bits plus carry plus
– for what inputs is
S=1 Cout = 1 x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z (cin) 0 1 0 1 0 1 0 1 S Cout S = x’y’z + x’yz’ + xy’z’ + xyz Cout = x’yz + xy’z + xyz’ + xyz Full Adder Full z(cin) x S = x’y’z + x’yz’ + xy’z’ + xyz Cout= xy + yz + xz y cout Building Blocks of ALUs Building
AND: c = ab a b c OR: c = a+b a b c NOT: c = a a s ° c multiplexor: control (s) selects input to output a b 0 1 c Review: The Multiplexor
Selects one of the inputs to be the output, based on a control Selects input
S note: we call this a 2-input mux even though it has 3 inputs!
C A B 0 1 Lets build our ALU using a MUX: Lets Different Implementations
Not easy to decide the “best” way to build something Not
– Don't want too many inputs to a single gate – Don’t want to have to go through too many gates – for our purposes, ease of comprehension is important 1-bit ALU for addition:
Possible Implementation (sum-of-products): Possible
CarryIn a Sum b cout = a b + a cin + b cin sum = a xor b xor cin
sum = a XOR b XOR c: XOR gate outputs 1 iff an odd number of input signals is 1 cin CarryOut hardware for carryout a b cout What about subtraction (a – b) ? What
How do we negate? How
– Two's complement approach: just negate b and add 1.
a 0 Binvert Operation CarryIn A very clever solution: very
1 Result b 0 1 2 CarryOut Different Implementations
1-bit ALU for addition:
CarryIn a Sum b cout = a b + a cin + b cin sum = a xor b xor cin CarryOut How could we build a 1-bit ALU for add, and, and or? How How could we build a 32-bit ALU? How 1-bit ALU for add, and, or
• All operations are performed at the same time same as input signals propagate through the circuitry. • Desired output or result is selected by the mux.
b Operation CarryIn a 0 1 Result 2 CarryOut CarryIn Operation Building a 32 bit ALU Building
Connect n 1-bit adders => Connect n-bit adder Problems: Problems:
– time to add is proportional to number of bits – alternative: carry lookahead adder that we’ll see later a0 b0 CarryIn ALU0 CarryOut Result0 a1 b1 CarryIn ALU1 CarryOut Result1 a2 b2 CarryIn ALU2 CarryOut Result2 Design thus far is Design incomplete… a31 b31 CarryIn ALU31 Result31 ripple carry adder: cout of LSB can effect cout of MSB Tailoring the ALU to the MIPS Tailoring
Need to support the set-on-less-than Need instruction (slt) – slt is an arithmetic instruction – produces a 1 if rs < rt and 0 otherwise
1 a 0 Binvert Operation CarryIn – use subtraction: (a-b) < 0 implies a<b – add additional input to MUX to select slt How do we tell if the result was How negative?
a. Less Result b 0 1 3 + 2 CarryOut Supporting slt: Can we figure out the idea? Supporting additional input to MUX to select slt additional slt = 1 if rs < rt and 0 otherwise slt uses: (a-b) < 0 implies a < b uses:
– If result is negative, slt = 1 – Why not connect msb of adder result to lsb ?
b a Binvert Operation CarryIn 0 1 Result 0 1 2 add an additional output bit to MSB to add indicate sign Less 3 Set Overflow detection Overflow b. Binvert Operation CarryIn Binvert CarryIn Operation a 0 1 Result b 0 1 Less 3 2 a0 b0 CarryIn ALU0 Less CarryOut Result0 a1 b1 0 CarryIn ALU1 Less CarryOut Result1 a. CarryOut Set from MSB adder is Set connected to Less of LSB If a-b < 0, result will be If negative
– – – – MSB = 1, thus set = 1 Less of LSB = 1 Less of remaining bits = 0 slt result = 1 a2 b2 0 CarryIn ALU2 Less CarryOut Result2 CarryIn a31 b31 0 CarryIn ALU31 Less Result31 Set Overflow Addition/Subtraction Addition/Subtraction
Overflow occurs when result will not fit in available bits Overflow when adding operands when
– occurs when carry into sign bit – Can’t if operands have different signs. why? If subtracting If
– occurs when carry out of sign bit – Can’t occur when signs are same. why? Effects of Overflow
An exception (interrupt) occurs An
– Control jumps to predefined address for exception – Interrupted address is saved for possible resumption Details based on software system / language Details
– e.g. Ada lets programmer explicitly describe what to do if exception. – Any idea why? Don't always want to detect overflow Don't
—MIPS instructions: addu, addiu, subu addu Overflow Overflow
Why wouldn’t overflow w/ unsigned numbers matter Why in many cases? Overflow Overflow
Why wouldn’t overflow w/ unsigned numbers matter Why in many cases?
– immediates typically used for manipulating address i.e. when n = 4, we can subtract 2 from 10 by adding 14: 1010 1110 This generates overflow, but we 1000 would not want a trap to be
generated. Overflow Detection Logic Overflow
Carry into MSB xor Carry out of MSB Carry
– For N-bit ALU: Overflow = CarryIn[N - 1] XOR CarryOut[N - 1]
CarryIn0 A0 B0 A1 B1 A2 B2 A3 B3 X 1-bit ALU CarryIn1 Result0 CarryOut0 0 0 1 1 Y 0 1 0 1 X XOR Y 0 1 1 0 1-bit Result1 ALU CarryIn2 CarryOut1 1-bit ALU CarryIn3 1-bit ALU CarryOut3 Result3 Result2 Overflow Tailoring the ALU to the MIPS Tailoring
Bnegate Operation Support test for equality Support (beq $t5, $t6, $t7)
– use subtraction: (a-b) = 0 implies a = b – add hardware to OR outputs of each ALU and invert
Why does this work? a0 b0 CarryIn ALU0 Less CarryOut Result0 a1 b1 0 CarryIn ALU1 Less CarryOut Result1 Zero a2 b2 0 CarryIn ALU2 Less CarryOut Result2 a31 b31 0 CarryIn ALU31 Less Result31 Set Overflow Test for equality Test
Bnegate Operation Notice control lines: Notice
a0 b0 000 001 010 110 111 = = = = = and or add subtract slt CarryIn ALU0 Less CarryOut Result0 a1 b1 0 CarryIn ALU1 Less CarryOut Result1 Zero a2 b2 0 CarryIn ALU2 Less CarryOut Result2 •Note: zero is a 1 when the result is zero! NOTE: When we want to subtract, we set Binvert = 1, CarryIn = 1. Therefore, combine into 1 control line: Bnegate. a31 b31 0 CarryIn ALU31 Less Result31 Set Overflow Conclusion Conclusion
We can build an ALU to support the MIPS We instruction set
– key idea: use multiplexor to select the output we want – we can efficiently perform subtraction using two’s complement – we can replicate a 1-bit ALU to produce a 32-bit ALU Conclusion Conclusion
Important points about hardware Important
– all of the gates are always working – the speed of a gate is affected by the number of inputs to the gate – the speed of a circuit is affected by the number of gates in series (on the “critical path” or the “deepest level of logic”) However, clever changes to organization can improve However, performance (similar to using better algorithms in software) ...
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