L6_instr_isa - CS 324 Computer CS Architecture Lecture 5...

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Unformatted text preview: CS 324 Computer CS Architecture Lecture 5: Memory Access/ Instructions Assembly Language Assembly Basic job of a CPU: execute lots of instructions. Basic instructions Instructions are the primitive operations that the CPU Instructions may execute. Different CPUs implement different sets of instructions. Different The set of instructions a particular CPU implements is an Instruction Set Architecture (ISA). Instruction – Examples: Intel 80x86 (Pentium 4), IBM/Motorola PowerPC (Macintosh), MIPS, Intel IA64, ... Instruction Set Architectures Instruction Early trend: add more and more instructions to new Early CPUs to do elaborate operations – VAX architecture had an instruction to multiply polynomials! RISC philosophy (Cocke IBM, Patterson, Hennessy, RISC 1980s) – Reduced Instruction Set Computing – Keep the instruction set small and simple – makes it easier to build fast hardware. – Let software do complicated operations by composing simpler ones. MIPS Architecture MIPS MIPS – semiconductor company that MIPS built one of the first commercial RISC architectures We’ll study MIPS architecture in some We detail 1400 Why MIPS instead of Intel 80x86? Why – MIPS is simple, elegant. Don’t want to get bogged down in gritty details. – MIPS widely used in embedded apps, x86 little used in embedded, and more embedded computers than PCs 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 Other SPARC Hitachi SH PowerPC Motorola 68K MIPS IA-32 ARM 1998 1999 2000 2001 2002 Instructions Instructions Language of the Machine Language More primitive than higher level languages More e.g., no sophisticated control flow Very restrictive Very e.g., MIPS Arithmetic Instructions – Perform only 1 operation – Have exactly 3 variables – Operands must be in registers (Load/Store architecture) Assembly Variables: Registers Assembly Unlike HLL like C or Java, assembly cannot use Unlike variables – Why not? Keep Hardware Simple Assembly Operands are registers Assembly – limited number of special locations built directly into the hardware – operations can only be performed on these! Benefit: Since registers are directly in hardware, they Benefit: are very fast (faster than 1 billionth of a second) MIPS arithmetic MIPS All instructions have 3 operands All Operand order is fixed (destination first) Operand Example: C code: A=B+C MIPS code: add $s0, $s1, $s2 ($s0 => register) ($s0 MIPS arithmetic MIPS Design Principle 1: simplicity favors regularity. Design Why? Of course this complicates some things... Of C code: A = B + C + D; E = F - A; MIPS arithmetic MIPS Operands must be registers Operands – Drawback: Since registers are in hardware, there are a predetermined number of them (only 32 registers provided) – Solution: MIPS code must be very carefully put together to efficiently use registers Design Principle 2: smaller is faster. Design Why? Each MIPS register is 32 bits wide Each – Groups of 32 bits called a word in MIPS Assembly Variables: Registers Assembly Registers are numbered from 0 to 31 Registers Each register can be referred to by number or name Each – Number references: $0, $1, $2, … $30, $31 By convention, each register also has a name to make By it easier to code: $16 - $23 $s0 - $s7 $s0 (correspond to C variables) $8 - $15 $t0 - $t7 $t0 (correspond to temporary variables) In general, use names to make your code more In readable C, Java variables vs. C, registers In C (and most High Level Languages) variables In declared first and given a type – Example: int fahr, celsius; int char a, b, c, d, e; Each variable can ONLY represent a value of the type it Each was declared as (cannot mix and match int and char int char variables). In Assembly Language, the registers have no type; In operation determines how register contents are treated Registers vs. Memory Registers Arithmetic instructions operands must be registers Arithmetic — only 32 registers provided Compiler associates variables with registers Compiler What about programs with lots of variables? What • place in memory (“register spilling”) Datapath Processor Control Memory Input Output I/O Memory Organization Memory 0 1 2 3 4 5 6 ... 8 bits of data 8 bits of data 8 bits of data 8 bits of data 8 bits of data 8 bits of data 8 bits of data Viewed as a large, single-dimension array, with an Viewed address. A memory address is an index into the array memory "Byte addressing": the index points to a byte of "Byte memory. Memory Organization Memory Bytes are nice, but most data items use larger "words" Bytes For MIPS, a word is 32 bits or 4 bytes. For 0 4 8 12 ... 32 bits of data 32 bits of data 32 bits of data 32 bits of data Registers hold 32 bits of data – 232 bytes with byte addresses from 0 to 232-1 – 230 words with byte addresses 0, 4, 8, ... 232-4 Endianess = byte order of a word address Endianess – Big Endian leftmost byte is word address – Little Endian: rightmost byte is word address Instructions Instructions Load and store instructions Load Example: (does anyone remember from C how an array is Example: addressed?) C code: MIPS code: A[8] = h + A[8] ; lw $t0, 32($s3) add $t0, $s2, $t0 sw $t0, 32($s3) Store word has destination last Store Remember arithmetic operands are registers, not memory! Remember Our First Example Our Can we figure out the code? Can swap(int v, int k); { int temp; temp = v[k] v[k] = v[k+1]; v[k+1] = temp; } Remember: lw loads words, but memory is Byte addressable! swap: muli $t2, $s5, 4 add $t2, $s4, $t2 lw $t15, 0($t2) lw $t16, 4($t2) sw $t16, 0($t2) sw $t15, 4($t2) jr $t31 So far we’ve learned: So MIPS MIPS — loading words but addressing bytes – words always start at addresses that are multiples of 4 — arithmetic on registers only Instruction Instruction add $s1, $s2, $s3 sub $s1, $s2, $s3 lw $s1, 100($s2) sw $s1, 100($s2) Meaning $s1 = $s2 + $s3 $s1 = $s2 – $s3 $s1 = Memory[$s2+100] Memory[$s2+100] = $s1 Machine Language Instructions, like registers and words of data, are 32 bits Instructions, – Example: add $t0, $s1, $s2 add – registers have values, $t0=9, $s1=17, $s2=18 $t0=9, Instruction Format: Instruction 000000 10001 10010 01001 00000 100000 op rs rt rd shamtfunct Can you guess what the field names stand for? Can Machine Language Consider the load-word and store-word instructions: Consider – What would the regularity principle have us do? op(6) rs(5) rt(5) rd(5)shamt funct – Example: lw $t0, 32($s2) lw hint: how much space do we have to specify operands? Machine Language New principle (3): Good design demands a compromise Introduce a new type of instruction format I-type for data transfer instructions: lw $t0, 32($s2) 35 op(6) 18 rs(5) 9 rt(5) 32 16 bit number other format was R-type for register op(6) rs(5) rt(5) rd(5)shamt funct Multiple formats complicate hardware, but complexity is reduced by keeping formats similar How are they distinguished? Stored Program Concept Instructions are bits Instructions Programs are stored in memory Programs — to be read or written just like data Processor Memory memory for data, programs, compilers, editors, etc. Fetch & Execute Cycle Fetch – Instructions are fetched and put into a special register – Bits in the register "control" the subsequent actions – Fetch the “next” instruction and continue Stored Program Concept Treating instructions the same way as data simplifies: Treating – Memory hardware Same memory technology used for data AND programs Same – Software of computer systems Compilers can translate HLL code (convenient for humans) into Compilers machine code (convenient for machines) Control Flow Decision making instructions Decision – alter the control flow i.e., change the "next" instruction to be executed MIPS conditional branch instructions: MIPS bne $t0, $t1, Label beq $t0, $t1, Label Example: Example: if (i==j) h = i + j; bne $s0, $s1, Label add $s3, $s0, $s1 Label: .... Assembler relieves the compiler from calculating Assembler branch addresses Control Flow MIPS unconditional branch instructions: MIPS j label – Are always taken – J-type to distinguish from conditional branch Example: Example: J op 26 bit address if (i!=m) h=i+m; else h=i-m; beq $s4, add $s3, j Lab2 Lab1:sub $s3, Lab2:... $s5, Lab1 $s4, $s5 $s4, $s5 So far: So Instruction Instruction add $s1,$s2,$s3 sub $s1,$s2,$s3 lw $s1,100($s2) sw $s1,100($s2) bne $s4,$s5,L beq $s4,$s5,L j Label Meaning $s1 = $s2 + $s3 $s1 = $s2 – $s3 $s1 = Memory[$s2+100] Memory[$s2+100] = $s1 Next instr. is at Label if $s4 != $s5 Next instr. is at Label if $s4 = $s5 Next instr. is at Label Formats: Formats: R I J op op op rs rs rt rt rd shamt funct 16 bit address 26 bit address Control Flow We have: beq, bne, what about Branch-if-less-than? We Recall slt: Recall slt $t0, $s1, $s2 if $s1 < $s2 then slt $t0 = 1 else $t0 = 0 Can use this instruction to build "blt $s1, $s2, Label" Can slt $t0, $s2, $s1 slt bne $t0, $zero, Label # if $s2< $s1, $t0 = 1, else $t0 = 0 Control Flow Control Control instructions: beq, bne, slt Control – Can build general control structures w/ beq, bne – slt is used to implement comparisons other than equality Note that the assembler needs a register to do this Note – there are policy of use conventions for registers Name $zero $v0-$v1 $a0-$a3 $t0-$t7 $s0-$s7 $t8-$t9 $gp $sp $fp $ra Register number 0 2-3 4-7 8-15 16-23 24-25 28 29 30 31 Usage the constant value 0 values for results and expression evaluation arguments temporaries saved more temporaries global pointer stack pointer frame pointer return address Register 1 ($at) reserved for assembler, 26-27 for OsS Constants Small constants used frequently (50% of operands) Small e.g., A = A + 5; B = B + 1; C = C - 18; Solutions? Solutions? – put 'typical constants' in memory and load them. – create hard-wired registers (e.g. $zero) for constants like 1. MIPS Instructions: MIPS addi $29, $29, 4 andi $29, $29, 6 ori $29, $29, 4 Design Principle: Make the common case fast. Which Design Which format? Logical Operations: Shifting Logical Facilitates examination of individual bits or bytes Facilitates Shifting left or right = mult. or div. by power of 2 Shifting sll or slr (shift left/right logical) sll slr – sll $t1, $s0, 8 => shift the value in $s0 left by 8 and store in $t1 $s0: 0000 0000 0000 0000 0000 0000 0001 1011 $t1: 0000 0000 0000 0000 0001 1011 0000 0000 8 R-type: 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits op rs rt rd sh.amt funct Logical Operations: AND/ OR Logical bit-by-bit operation bit – AND leaves 1 iff both operands’ bits are 1 forces 0s where they occur in bit pattern forces referred to as a Mask, since some bits are concealed referred Mask – OR leaves a 1 if either operands’ bits are 1 forces 1s where they occur in mask, 0 leaves bits unchanged forces Can use a mask to set bits with a logical op, but must Can first set bits in the mask … so why can’t we just set bits directly without logical op? AND/ OR AND/ Lets assume we want to clear the LSB: 0000 0000 1010 0111 We want to AND w/ fffehex: 0000 0000 1010 0111 1111 1111 1111 1110 But, if some of the high order bits are set, must create a 32-bit constant: 0000 0000 1000 0010 0000 0000 1010 0111 1111 1111 1111 1111 1111 1111 1111 1110 How about larger constants? We'd like to be able to load a 32 bit constant into a register We'd Must use two instructions, new "load upper immediate" Must instruction – lui $t0, 1010101010101010 1010101010101010 0000000000000000 filled with zeros Then must get the lower order bits right, i.e., Then – ori $t0, $t0, 1010101010101010 1010101010101010 0000000000000000 ori 1010101010101010 1010101010101010 0000000000000000 1010101010101010 Addressing Modes Addressing Immediate: operand is a binary value coded in the Immediate: in instruction Indexed/Base: Instruction specifies base address and Indexed/Base: offset which is added to base to get address of item Register: value is in a register, instruction contains Register: register number PC-Relative: address is the sum of the PC and a constant PC in the instruction Pseudodirect: Jump address is 26 bits of the instruction Pseudodirect + upper bits of PC Addresses in Branches Instructions: Instructions: bne $t4,$t5,Label beq $t4,$t5,Label Next instruction is at Label if $t4!= $t5 Next instruction is at Label if $t4 = $t5 $t4 Formats: Formats: I op rs rt 16 bit address Addresses are 16 bits Addresses – However, 16 bits only enables a maximum program size of 2^16, which is not practical for most programs How is this problem addressed? How – How is it done for lw or sw? (think of array accesses, for example) Addresses in Branches 16-bits: How is this problem addressed? 16 – How is it done for lw or sw? (think of array accesses, for example) Could specify a register and add it to address Could – use Instruction Address Register (PC = program counter) – Works well for conditionals since most branches are local (principle of locality) typically loops or if statements going roughly 16 instructions away typically loops if I op rs rt 16 bit address Addresses in Branches Jump/Jump-and-link instructions invoke procedures Jump/Jump – Not found near call, so other form of addressing needed Jump instructions just use high order bits of PC Jump Instructions: Instructions: j 10000 # go to location 10000 J op 26 bit address Assembly Language vs. Machine Language Assembly provides convenient symbolic representation Assembly – much easier than writing down numbers – e.g., destination first Machine language is the underlying reality Machine – e.g., destination is no longer first Assembly can provide 'pseudoinstructions' Assembly – e.g., “move $t0, $t1” exists only in Assembly – would be implemented using “add $t0,$t1,$zero” When considering performance you should count real When instructions Summary Summary Instructions are the words of a machine language, Instructions machine’s vocabulary is its instruction set Instruction operands are registers Instruction – MIPS has 32 32-bit registers (smaller is faster) Data must be transferred to and from memory Data Words must always start at byte addresses that are Words multiples of 4 Overview of MIPS simple instructions all 32 bits wide simple very structured, no unnecessary baggage very only three instruction formats only R I J op op op rs rs rt rt rd shamt funct 16 bit address 26 bit address rely on compiler to achieve performance rely – what are the compiler's goals? Efficient use of registers! help compiler where we can help To summarize: To MIPS operands Name 32 registers Example $s0-$s7, $t0-$t9, $zero, $a0-$a3, $v0-$v1, $gp, $fp, $sp, $ra, $at Memory[0], Memory[4294967292] Comments Fast locations for data. In MIPS, data must be in registers to perform arithmetic. MIPS register $zero always equals 0. Register $at is reserved for the assembler to handle large constants. Accessed only by data transfer instructions. MIPS uses byte addresses, so sequential words differ by 4. Memory holds data structures, such as arrays, and spilled registers, such as those saved on procedure calls. 230 memory Memory[4], ..., words Category add Instruction MIPS assembly language Example Meaning add $s1, $s2, $s3 $s1 = $s2 + $s3 sub $s1, $s2, $s3 addi $s1, $s2, 100 lw $s1, 100($s2) sw $s1, 100($s2) lb $s1, 100($s2) sb $s1, 100($s2) lui $s1, 100 beq bne slt slti j jr jal $s1, $s2, 25 $s1, $s2, 25 $s1, $s2, $s3 $s1 = $s2 - $s3 $s1 = $s2 + 100 $s1 = Memory[$s2 + 100] Memory[$s2 + 100] = $s1 $s1 = Memory[$s2 + 100] Memory[$s2 + 100] = $s1 $s1 = 100 * 216 if ($s1 == $s2) go to PC + 4 + 100 if ($s1 != $s2) go to PC + 4 + 100 if ($s2 < $s3) $s1 = 1; else $s1 = 0 else $s1 = 0 Comments Three operands; data in registers Three operands; data in registers Arithmetic subtract Data transfer add immediate load word store word load byte store byte load upper immediate branch on equal branch on not equal Used to add constants Word from memory to register Word from register to memory Byte from memory to register Byte from register to memory Loads constant in upper 16 bits Equal test; PC-relative branch Not equal test; PC-relative Compare less than; for beq, bne Compare less than constant Conditional branch set on less than set less than immediate jump jump register jump and link $s1, $s2, 100 if ($s2 < 100) $s1 = 1; 2500 $ra 2500 Unconditional jump go to 10000 Jump to target address go to $ra For switch, procedure return $ra = PC + 4; go to 10000 For procedure call 1. Immediate addressing op rs rt Immediate 2. Register addressing op rs rt rd ... funct Registers Register 3. Base addressing op rs rt Address Memory Register + Byte Halfword Word 4. PC-relative addressing op rs rt Address Memory PC + Word 5. Pseudodirect addressing op Address Memory PC Word ...
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This note was uploaded on 02/15/2010 for the course CS 324 taught by Professor Lballesteros during the Fall '08 term at Mt. Holyoke.

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