L9_control

L9_control - CS324: Computer CS324: Architecture Lecture 9:...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: CS324: Computer CS324: Architecture Lecture 9: Single Cycle/ Control 3b: Add & Subtract 3b: R[rd] <- R[rs] op R[rt] Example: addu rd, rs, rt R[rd – Ra, Rb, and Rw come from instruction’s rs, rt, and rd fields – ALUctr and RegWr: control logic after decoding the instruction 31 op 6 bits 26 rs 5 bits 21 rt 5 bits 16 rd 5 bits 11 shamt 5 bits 6 funct 6 bits 0 Rd Rs Rt RegWr 5 5 5 busW 32 Clk Rw Ra Rb 32 32-bit Registers ALUctr busA 32 busB 32 ALU Result 32 3c: Logical Operations with Immediate R[rt] <- R[rs] op ZeroExt[imm16] ] R[ 31 26 op 6 bits 31 0000000000000000 16 bits Rd Rs Rt RegWr 5 5 5 busW 32 Clk Rw Ra Rb 32 32-bit Registers ALUctr Rd Rt RegDst busA Mux Rs 32 RegWr 5 5 5 Result 32 busA Rw Ra Rb busB busW 32 32 32-bit 32 32 Registers busB Clk 32 imm16 ALU ZeroExt 16 32 ALUSrc 21 rs 5 bits 16 rt 5 bits 16 15 11 immediate 16 bits rd? immediate 16 bits 0 I-Type 0 ALU ctr Result 32 ALU Mux 3d: Load Operations R[rt] <- Mem[R[rs] + SignExt[imm16]] R[ lw rt, rs, imm16 31 Rd RegDst Mux Rt Rs 55 busA 32 busB 32 32 ALUSrc Mux 26 op 6 bits 21 rs 5 bits ALUc tr ALU 16 rt 5 bits Example: 11 0 immediate 16 bits rd RegWr 5 busW 32 Clk Rw Ra Rb 32 32-bit Registers W_Src 32 MemWr WrEn Adr Mu x Extender imm16 16 Data In 32 Clk Data Memory 32 ExtOp 3e: Store Operations Mem[ R[rs] + SignExt[imm16] <- R[rt] ] Example: Mem sw rt, rs, imm16 31 26 op 6 bits Rd RegDst Mux 5 Rs Rt 5 busA 32 busB 32 32 Mux ALU 32 Mu x WrEn Adr Data In 32 Clk ALUSrc Data Memory 0 => RegWr 5 busW 32 Clk Rt 21 rs 5 bits ALUct r 16 rt 5 bits MemWr immediate 16 bits W_Src 0 Rw Ra Rb 32 32-bit Registers Extender imm16 32 16 ExtOp 3f: The Branch Instruction 3f: 31 26 op 6 bits 21 rs 5 bits 16 rt 5 bits immediate 16 bits 0 beq rs, rt, imm16 beq – mem[PC] memory Fetch the instruction from – Equal <- R[rs] == R[rt] Calculate the branch condition Rt – Rs – if (COND eq 0) – else PC <- PC + 4 PC Calculate the next instruction’s address PC <- PC + 4 + ( SignExt(imm16) x 4 ) PC Datapath for Branch Operations beq rs, rt, imm16 beq condition (equal) 31 26 op rs 6 bits 5 bits Inst Address 4 Adder Mux Adder imm16 PC Ext nPC_sel 32 00 busW Clk PC Clk RegWr 5 Datapath generates 21 16 rt 5 bits immediate 16 bits Cond Rs Rt 5 busA 32 busB 32 Equal? 0 5 Rw Ra Rb 32 32-bit Registers Putting it All Together: A Single Cycle Datapath Inst Memory Adr nPC_sel RegDst Instruction<31:0> <21:25> Rs <16:20> Rt <11:15> Rd <0:15> Imm16 Equal ALUct MemWr MemtoReg r Rd Rt 10 5 4 Adder Mux Adder PC Ext 00 RegWr 5 busW 32 Clk Clk imm16 Rs Rt 5 busA Rw Ra Rb 32 32 32-bit Registers busB 0 32 Mux Extender 1 32 = ALU 32 WrEn Adr Data Memory 0 Mux PC imm16 32 Data In Clk 1 16 ExtOp ALUSrc Single-cycle Datapath Single MIPS makes design easier MIPS – Instructions same size – Source registers always in same place – Immediates same size, location – Operations always on registers/immediates Single cycle datapath Single – CPI=1 – Clock Cycle Time (CCT) is long CCT determined by longest instruction CCT Complicated operations (FP) really slow things down Complicated An Abstract View of the Critical Path Register file and ideal memory: Register – The CLK input is a factor ONLY during write operation – During read operation, behave as combinational logic: Address valid => Output valid after “access time.” Address Critical Path (Load Operation) = PC’s Clk-to-Q + Instruction Memory’s Access Time + Register File’s Access Time + ALU to Perform a 32-bit Add + Data Memory Access Time + Setup Time for Register File Write + Clock Skew Data Address Ideal Data In Clk Data Memory Ideal Instruction Memory Instruction Address Next Address 32 PC Instruction Rd Rs 5 5 Rt 5 Imm 16 A Rw Ra Rb 32 32-bit Registers 32 B 32 ALU 32 Clk Clk Processor Design Processor 5 steps to design a processor steps – 1. Analyze instruction set => datapath requirements – 2. Select datapath components, establish clock methodology – 3. Assemble datapath meeting the requirements – 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. – 5. Assemble the control logic Next: implementing control Next: Recap: The MIPS Subset Recap: ADD and subtract ADD – add rd, rs, rt – sub rd, rs, rt 31 26 op 6 bits 31 26 op 6 bits 21 rs 5 bits 21 rs 5 bits 16 rt 5 bits 16 rt 5 bits immediate 16 bits 11 rd 5 bits shamt 5 bits 6 funct 6 bits 0 0 OR Imm: OR – ori rt, rs, imm16 LOAD and STORE LOAD – lw rt, rs, imm16 – sw rt, rs, imm16 BRANCH: BRANCH: – beq rs, rt, imm16 Recap: A Single Cycle Datapath Recap: We have everything except control signals We – Today: how to generate the control signals Instruction<31:0> nPC_sel Rd RegDst Rt Rs Rt 5 5 Clk <11:15> <21:25> <16:20> Instruction Fetch Unit <0:15> 1 Mux 0 RegWr 5 busW 32 Clk busA Rw Ra Rb 32 32 32-bit Registers busB 0 32 Extender 1 32 ALUct r ALU Rt Zero 32 Rs Rd Imm16 MemtoReg 0 Mux MemWr Mux Data In 32 Clk 32 WrEn Adr Data Memory 1 imm16 16 ALUSrc ExtOp An Abstract View of the Implementation An Ideal Instruction Memory Instruction Address Next Address 32 PC Control Instruction Rd Rs 5 5 Rt 5 A Rw Ra Rb 32 32-bit Registers 32 32 B ALU Data Address Data In Clk Data Out Control Signals Conditions Ideal Data Memory Clk Clk 32 Datapath Logical vs. Physical Structure Logical Step 4: Given Datapath: RTL -> Control Step Goal: design control unit that takes opcode bits and generates the control signals that will allow the specified instruction to execute. Instruction<31:0> <21:25> <16:20> <11:15> <21:25> Inst Memory Adr <0:15> Op Fun Rt Rs Rd Imm16 Control nPC_sel RegWr RegDst ExtOp ALUSrc ALUctr MemWr MemtoReg Equal DATA PATH Control Control Selecting the operations to perform (ALU, read/write, etc.) Selecting Controlling the flow of data (multiplexor inputs) Controlling Information comes from the 32 bits of the instruction Information Example: Example: add $8, $17, $18 000000 10001 10010 Instruction Format: 01000 00000 100000 op rs rt rd shamt funct ALU's operation based on instruction type and function code ALU's Control Control ALU performs a specific function for ea instruction class ALU All control signals, except PCSrc, can be set based solely All on opcode field of instruction Need control circuitry that: Need – takes opcode and funct fields as input – outputs appropriate 3-bit ALU control input Processor has 2 distinct circuits for this: Processor 1. Main controller: takes 5-bit opcode and produces 2-bit field, ALUOp 2. ALU controller: uses the ALUOp signal & 6-bit funct field to produce the 3-bit ALU control signal Control e.g., what should the ALU do with this instruction e.g., Example: lw $1, 100($2) Example: 35 2 1 100 op rs rt 16 bit offset ALU control input ALU 000 AND 001 OR 010 add 110 subtract 111 set-on-less-than Why isn’t 011 used to represent subtract? Why ALU Control ALU Binvert CarryIn Operation Recall binvert &carry-in Recall Result0 a0 b0 CarryIn ALU0 Less CarryOut – Both 1 for subtract – Both 0 for add, OR, AND a1 b1 0 CarryIn ALU1 Less CarryOut Result1 Combined to form 1 control Combined input: Bnegate – This is bit 3 of ALU control 000 AND 001 OR 010 add 110 subtract 111 slt a2 b2 0 CarryIn ALU2 Less CarryOut Result2 CarryIn a31 b31 0 CarryIn ALU31 Less Result31 Set Overflow RTL: The add Instruction RTL: add add rd, rs, rt add 31 op 6 bits 26 rs 5 bits 21 rt 5 bits 16 rd 5 bits 11 shamt 5 bits 6 funct 6 bits 0 – mem[PC] Fetch the instruction from memory The actual operation Calculate the next instruction’s address – R[rd] <- R[rs] + R[rt] – PC <- PC + 4 Instruction Fetch Unit at Beginning of Add Instruction Add Fetch the instruction from Instruction memory: Fetch Instruction <- mem[PC] – This is the same for all instructions Inst Memory Adr nPC_sel Instruction<31:0> 4 Adder Mux Adder 00 PC Clk imm16 PC Ext The Single Cycle Datapath during Add Add 31 op 26 rs 21 rt 16 rd 11 shamt 6 funct 0 R[rd] <- R[rs] + R[rt] R[rd Instruction<31:0> nPC_sel= +4 Rd RegDst = 1 Rt Rs Rt 5 5 1 Mux 0 Clk <21:25> <16:20> <11:15> Instruction Fetch Unit <0:15> ALUctr = Add RegWr = 1 5 busW 32 Clk Rt Zero busA Rw Ra Rb 32 32 32-bit Registers busB 0 32 Mux Extender 1 32 Imm16 MemtoReg = 0 MemWr = 0 0 Mux 32 Rs Rd imm16 Data In 32 Clk ALU 32 WrEn Adr Data Memory 1 16 ALUSrc = 0 ExtOp = x branch and jump must also be set to 0 Instruction Fetch Unit at the End of Add PC <- PC + 4 PC – This is the same for all instructions except: Branch and Jump Inst Memory Adr nPC_sel Instruction<31:0> 4 Adder Mux Adder 00 PC updated at every cycle, therefore no write enable needed. Picture is always the same except for a jump or branch PC imm16 Clk The Single Cycle Datapath during Or Immediate 31 op 26 rs 21 rt 16 immediate 0 R[rt] <- R[rs] or ZeroExt[Imm16] R[rt nPC_sel= +4 RegDst = 0 Rt 1 Mux 0 Rs Rt 5 5 Rd Clk Instruction<31:0> <11:15> <21:25> Rt Zero ALU 32 WrEn Adr Data Memory 32 <16:20> Instruction Fetch Unit <0:15> RegWr = 1 5 busW 32 Clk busA Rw Ra Rb 32 32 32-bit busB Registers 0 32 Extender 1 32 imm16 ALUctr = Or Rs Rd Imm16 MemtoReg = 0 0 Mux 1 MemWr = 0 Mux Data In 32 Clk 16 ALUSrc = 1 ExtOp = 0 The Single Cycle Datapath during Load 31 op 26 rs 21 rt 16 immediate 0 R[rt] <- Data Memory {R[rs] + SignExt[imm16]} R[rt nPC_sel= +4 RegDst = 0 Rt 1 Mux 0 Rs Rt 5 5 Rd Clk Instruction<31:0> <11:15> <21:25> <16:20> Instruction Fetch Unit <0:15> RegWr = 1 5 busW 32 Clk ALUctr = Add ALU Rt Zero 32 busA Rw Ra Rb 32 32 32-bit busB Registers 0 32 Extender 1 32 imm16 Imm16 MemtoReg = 1 MemWr = 0 0 Mux Rs Rd Mux Data In 32 Clk 16 WrEn Adr Data Memory 1 32 ALUSrc = 1 ExtOp = 1 again branch and jump must also be set to 0 ...
View Full Document

This note was uploaded on 02/15/2010 for the course CS 324 taught by Professor Lballesteros during the Fall '08 term at Mt. Holyoke.

Ask a homework question - tutors are online