L11_ControlMicro - CS324 Computer CS324 Architecture...

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Unformatted text preview: CS324: Computer CS324: Architecture Lecture 11: Control, Microprogramming Performance Evaluation Performance What is the average CPI? What – state diagram gives CPI for each instruction type – workload gives frequency of each type Type Arith/Logic Load Store branch CPIi for type 4 5 4 3 Frequency 40% 30% 10% 20% Average CPI: CPIi x freqIi 1.6 1.5 0.4 0.6 4.1 Graphical Representations Graphical of Control As instruction set becomes more complex As – Number of states per instruction can vary widely could be between 1-20 cycles per instruction could – FSM can contain hundreds of states easier to make mistakes! easier Alternative: Microprogramming Alternative: Microprogramming Microprogramming Think of control signals that must be asserted as a Think μinstruction to be executed by the datapath – A μinstruction defines the control signals that must be asserted in a given state – Executing a μinstruction has the effect of asserting the control signals specified by the μinstruction Need a method to specify μinstruction sequencing Need – Sequential – branch Controller Design construct a simple construct “microsequencer” w/counter Control reduces to programming Control this very simple device – microprogramming ≈ control signals – symbolic representation of control that will be translated by a program to control logic sequencer control datapath control microinstruction micro-PC sequencer Microcode Microcode Combine states, registers, additional control logic, Combine and ROM to get a FSM called a μcode engine. – opcode from IR becomes jump address into ROM – μPC can be used to step thru series of fetches from ROM beginning with this address – each fetch results in control signals being sent out Alternative to μPC: each μinstruction explicitly Alternative specifies the address of its successor – one of the fields of the μinstruction may be the address of the next μinstruction “Macroinstruction” Interpretation Main Memory ADD SUB AND User program plus Data this can change! . . . DATA execution unit CPU control memory one of these is mapped into one of these AND microsequence e.g., Fetch Calc Operand Addr Fetch Operand(s) Calculate Save Answer(s) Microcode Instruction Format Microcode Simplest form: each bit represents a control signal Simplest sent to datapath – bits in the μinstruction are connected to control wires, thus causing actions to occur in the datapath control signal outputs 0 next instruction 23 24 31 Microcode Instruction Format Microcode Format designs are often classified by the width of Format the word employed. – horizontal: a very wide word that contains all of the control signals necessary to drive the system – vertical: a narrower word, with a sequence of μinstructions driving all of the control signals vertical μinstruction seems inherently slower – vertical it takes a sequence of operations to accomplish what the horizontal μinstruction can do in a single cycle. But… Vertical Instruction Format Vertical in many cases, individual control lines are asserted only in in certain minor states if control grouped by minor state, we can reuse some bits of the if micro-word by having their outputs first fed to a "demultiplexer" that steers them to the proper signal lines according to the current minor state In effect the microinstruction format is using multiple instruction In formats to reduce redundancy state dependent state field fixed signal field next instruction demultiplexor state 0 signals state 1 signals state 2 signals Horizontal vs. Vertical Microprogramming Horizontal •Most microprogramming-based controllers vary between: •horizontal organization (1 control bit per control point) •vertical organization (fields encoded in the control memory and must be decoded to control something) Horizontal + more control over the potential parallelism of operations in the datapath uses up lots of control store... this can be considerable Vertical + easier to program, not very different from programming a RISC machine in assembly language extra level of decoding may slow the machine down Designing a Microinstruction Set Designing 1) Start with list of control signals 2) Group signals together that make sense: called “fields” 3) Place fields in some logical order (e.g., ALU operation & ALU operands first and microinstruction sequencing last) 4) Create a symbolic legend for the microinstruction format, showing name of field values and how they set the control signals – Use computers to design computers 5) To minimize the width, encode operations that will never be used at the same time Legacy Software and Microprogramming Legacy IBM bet company on 360 ISA: single instruction set IBM for many classes of machines – (8-bit to 64-bit) Stewart Tucker stuck with job of what to do about Stewart software compatibility – If μprogramming allows same instruction set on many different μarchitectures, then why not multiple μprograms to do multiple instruction sets on the same μarchitecture? Legacy Software and Microprogramming Legacy Coined term “emulation”: instruction set interpreter in Coined microcode for non-native instruction set Very successful in early years of IBM 360: Very it was hard to know whether old instruction set or new instruction set was more frequently used Why Microcode? Why Most RISC designs are sufficiently regular that CU Most can be constructed from a FSM built with control logic For CISC, speed decrease was outweighed by need to For manage complexity of controlling the architecture – lg num instruction types, many addressing modes, etc – 1000s of logic expressions => large irreg logic on chip – mistake discovered later may require re-simplifying entire design and possibly chip redesign recall pentium bug!!! recall Why Microcode? Why Errors occur pretty regularly… Errors – reduces cost of correcting errors – Bug-fix to μcoded controller ≡ changing ROM – easier to enhance since unused opcodes can be turned into new machines by extending μcode – simplifies the initial design Compatibility: many organizations, one ISA Compatibility: But … But – costly to implement – slower Control Control Whether represented as FS diagram or as μcode, translation Whether to hardware implementation is similar – Next-state function implemented by Encoding it in FSM Encoding Using an explicit sequencer Using – More efficient if # states is large and many consecutive states without branching May be implemented as May – ROMs: appropriate if control is stored in separate memory (Offchip) – PLAs: More efficient unless control function is very dense Summary Summary Disadvantages of the Single Cycle Processor Disadvantages – Long cycle time – Cycle time is too long for all instructions except the Load Multiple Cycle Processor: Multiple – Divide the instructions into smaller steps – Execute each step (rather than entire instr.) in 1 cycle Partition datapath into equal size chunks to minimize Partition cycle time Follow same 5-step method for designing “real” Follow processor Summary (cont’d) Summary Control is specified by finite state diagram Control State-diagrams easily captured by microsequencer State – simple increment & “branch” fields – datapath control fields Control design reduces to Microprogramming Control Control is more complicated with: Control – complex instruction sets Simple IS and powerful datapath => simple control Simple – could try to reduce hardware – rather go for speed => many instructions at once! Overview of Control Overview Control may be designed using one of several initial representations. The Control choice of sequence control, and how logic is represented, can then be determined independently; the control can then be implemented with one of several methods using a structured logic technique. Initial Representation Finite State Diagram Microprogram Sequencing Control Explicit Next State Function Logic Equations Microprogram counter + Dispatch ROMs Truth Tables Logic Representation Implementation Technique PLA “hardwired control” ROM “microprogrammed control” Exceptions user program Exception: System Exception Handler return from exception normal control flow: sequential, jumps, branches, calls, returns Exception = un-programmed control transfer Exception – system takes action to handle the exception must record the address of the offending instruction must – returns control to user must save & restore user state must Allows construction of a “user virtual machine” Allows What happens to an What Instruction with Exception? MIPS: defines instruction as having no effect if the MIPS: if instruction causes an exception. Certain classes of exceptions must prevent the Certain instruction from changing the machine state (esp. when Virtual Memory in use). This aspect of handling exceptions becomes complex This and potentially limits performance => why it is hard Two Types of Exceptions Two Interrupts: caused by external events Interrupts: – asynchronous to program execution – may be handled between instructions – simply suspend and resume user program Two Types of Exceptions Two Exceptions/Traps Exceptions/Traps – caused by internal events exceptional conditions (overflow) exceptional memory faults (non-resident page) memory – synchronous to program execution – condition must be remedied by the handler – instruction may be retried or simulated and program continued or program may be aborted MIPS convention: MIPS Exception: any unexpected change in control flow, without Exception: distinguishing internal or external; use the term interrupt only when the event is externally caused. Type of event I/O device request Invoke OS from user program Arithmetic overflow Using an undefined instruction Hardware malfunctions From where? MIPS terminology External Interrupt Internal Internal Internal Either Exception Exception Exception Exception or Interrupt Addressing the Exception Handler Traditional Approach: Interrupt Vector Traditional – Address to which control is transferred is based upon cause of interrupt iv_base – OS knows reason by address chosen cause handler code MIPS Approach: fixed entry MIPS – Control is always transferred to PC <– EXC_addr – Based on cause register value, OS selects address of code to execute – Actually very small table handler entry code iv_base cause Saving State Saving Push it onto the stack Push – Vax, 68k, 80x86 Save it in special registers Save – MIPS EPC (hold addr of affected instr), BadVaddr, Status/Cause (holds field indicating reason for ex) Shadow Registers Shadow – M88k – Save state in a shadow of the internal pipeline registers Additions to MIPS ISA Additions to support Exceptions? EPC–a 32-bit register used to hold the address of the EPC affected instruction. Cause–a register used to record the cause of the Cause exception. In the MIPS architecture this register is 32 bits, though some bits are currently unused. BadVAddr - register containing memory address at BadVAddr which memory reference occurred Status - interrupt mask and enable bits Status Additions to MIPS ISA to Additions support Exceptions? Control signals to write EPC, Cause, BadVAddr, and Control Status Be able to write exception addr to PC: incr mux to add Be another input const. value wired to 0xC0000000 (address of handler code) May have to undo PC = PC + 4, since want EPC to point May to offending instruction (not its successor); PC = PC - 4 Big Picture: user / system modes Big By providing two modes of execution (user/system) By it is possible for the computer to manage itself – OS is a special program that runs in the privileged mode and has access to all of the computer’s resources – presents “virtual resources” to each user that are more convenient than the physical resources files vs. disk sectors files virtual memory vs physical memory virtual – protects each user program from others Big Picture: user / system modes Big Exceptions allow the system to take an action in Exceptions response to events that occur while user program is executing – O/S begins at the handler How Control Detects How Exceptions in our FSM Undefined Instruction–detected when no next state is Undefined defined from state 1 for the op value. – We handle this exception by defining the next state value for all op values other than lw, sw, R-type, jmp, beq, and ori as new state 12. – Shown symbolically using “other” to indicate that the op field does not match any of the opcodes that label arcs out of state 1. Modification to the Control Specification Modification IR <= MEM[PC] PC <= PC + 4 undefined instruction EPC <= PC - 4 PC <= exp_addr cause <= 10 (RI) BEQ S <= A - B A <= R[rs] B <= R[rt] other R-type S <= A fun B ORi LW SW S <= A + SX S <= A op ZX S <= A + SX 0010 Equal PC <= PC + SX || 00 ~Equal overflow M <= MEM[S] MEM[S] <= B 0011 R[rd] <= S R[rt] <= S R[rt] <= M EPC <= PC - 4 PC <= exp_addr cause <= 12 (Ovf) How Control Detects Exceptions How in our FSM Arithmetic overflow: Overflow signal is used in the modified finite state machine to specify an additional possible next state – Recall logic in ALU to detect overflow – Overflow signal is provided as an output from the ALU. Challenge to design control of real machine Challenge – handling different interactions between instructions and other exception-causing events such that control logic remains small and fast. – Complex interactions makes the control unit the most challenging aspect of hardware design Summary Summary Control design reduces to Microprogramming Control Exceptions are the hard part of control Exceptions 1. Need to find convenient place to detect exceptions 2. branch to state or microinstruction that saves PC and invokes the operating system Summary Summary Control gets even harder Control – Pipelined CPUs support page faults on memory accesses which means Instruction cannot complete Instruction you must be able to restart the program at exactly the you instruction with the exception ...
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This note was uploaded on 02/15/2010 for the course CS 324 taught by Professor Lballesteros during the Fall '08 term at Mt. Holyoke.

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