L16VM - CS324: Computer Architecture CS324: Lecture 16:...

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CS324: Computer Architecture CS324: Computer Architecture Lecture 16: Virtual Memory
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Analyzing Multi Analyzing Multi - - level cache hierarchy level cache hierarchy Let miss rate at primary = 2%. How much faster will processor be if we add 2ry cache with 5ns access time for hits and misses And is large enough to reduce miss rate to main memory to 0.5%? For 1 level: CPI = 1 + For 1 level: CPI = 1 + mem mem stalls to MM = 1 + .02*400 = 9 stalls to MM = 1 + .02*400 = 9 Miss penalty to 2ry = 5ns/(.25ns/cycle) = 20 clock cycles Total CPI = 1+ 1ry stalls + 2ry stalls Total CPI = 1+ 1ry stalls + 2ry stalls = 1 + .02*20 +.005*400 = 3.4 = 1 + .02*20 +.005*400 = 3.4 Proc w/ 2ry cache is faster by 9/3.4 = 2.6 Proc w/ 2ry cache is faster by 9/3.4 = 2.6 Proc $ 2 DRAM $ L1 hit time L1 Miss Rate L1 Miss Penalty L2 hit time L2 Miss Rate L2 Miss Penalty CPI =1; 0.25ns clock 400 cycle Miss Penalty to main memory Total CPI = Base CPI + memory stalls
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And in Conclusion And in Conclusion ± Caching in general shows up over and over in computer systems – Filesystem cache – Web page cache – Game databases / tablebases – Software memoization –O t h e r s ? ± Big idea: if something is expensive but we want to do it repeatedly, do it once and cache the result. ± Cache design choices: – Write through v. write back – size of cache: speed v. capacity – direct-mapped v. associative – for N-way set assoc: choice of N – block replacement policy –2 nd level cache? –3
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Questions Questions 1. the cycle time of processors has decreased. (I.e., is closing) 2. A 2-way set-associative cache can be outperformed by a direct- mapped cache. 3. Larger block size lower miss rate ABC 0: FFF 1: FFT 2: FTF 3: FTT 4: TFF 5: TFT 6: TTF 7: TTT
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Answers Answers 1. the cycle time of processors has decreased. (I.e., is closing) 2. A 2-way set-associative cache can be outperformed by a direct- mapped cache. 3. Larger block size lower miss rate 1. That was was one of the motivation for caches in the first place -- that the memory gap is big and widening. 2. Sure, consider 4 byte caches with 1 byte blocks: 2-way and DM with the following workload: 0, 2, 0, 4, 2 2-way : 0m , 2m , 0h , 4m , 2m ; DM : 0m , 2m , 0h , 4m , 2h 3. Larger block size lower miss rate, true until a certain point, and then the ping-pong effect takes over ABC 0: FFF 1: FFT 2: FTF 3: FTT 4: TFF 5: TFT 6: TTF 7: TTT
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Memory Hierarchy Memory Hierarchy 1. Registers Fast storage internal to processor Speed = 1 CPU clock cycle Persistence = Few cycles Capacity ~ 0.1K to 2K Bytes 2. Cache Fast storage internal or external to processor Speed = A few CPU clock cycles Persistence = Tens to Hundreds of pipeline cycles, 0.5MB to 2MB 3. Main Memory Main storage usually external to processor, < 16GB
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This note was uploaded on 02/15/2010 for the course CS 324 taught by Professor Lballesteros during the Fall '08 term at Mt. Holyoke.

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L16VM - CS324: Computer Architecture CS324: Lecture 16:...

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