L18iMulti - CS324 Computer Architecture CS324 Computer...

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CS324: Computer Architecture CS324: Computer Architecture Lecture 18: Multicores & Multiprocessors
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Improving Performance Pipelining Instruction Level Parallelism (ILP) Out-of-order (uses register renaming) Deeper pipeline: more stages -> more instructions executing in parallel Multiple issue: multiple instructions issued per cycle. 3-6 per cycle typical. i d i ll ( il i ) d i ll ( i ) Determined statically (compile time) or dynamically (runtime) e.g. Superscalar Add more functional units or pipelines to CPU
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