E1-1 - Sedma Nacionalna Konferencija so Me|unarodno U~estvo...

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ALL-MOS LINEAR RESISTIVE GRIDS FOR SPATIAL VISUAL PROCESSING I: A THREE TRANSISTOR NONFLOATING ONE-PORT LINEAR RESISTOR Goce V. Shutinoski 1 1 “Ss. Cyril and Methodius” University – Institute of Electronics, Faculty of EE, Karpos 2 BB PO box 574, MK-1000 Skopje, Republic of Macedonia, E-mail: [email protected] Abstract – The paper presents a novel active resistor circuit composed of all-mos elements. The voltage mirroring technique implemented with MOS transistors exhibits performance of nonfloating linear resistive element. It comprises only three MOS transistors: two of them are enhancement type and the third is a depletion type MOS. The possibilities of controlling the variable resistance (tunability) are presented and simulation results are given. One substantial implementation of the circuit in all-MOS linear resistive grid for spatial retinotopic processing is also presented. Index terms — MOS VLSI, active resistors, resistive grid, nonfloating resistive port 1. INTRODUCTION The advances in VLSI MOS technology demand IC resistors to be fully designed and fabricated in the same semiconductor processing. Resistive elements can be implemented as physical resistors occupying large chip areas and because of large parasitic capacitance their applications are not economic and are limited to low frequency circuits, [1], [2]. Resistors synthesized by using MOS transistors are preferable in analog circuits design since they use smaller area fraction, parasitic capacitance is lower and they have controllable resistance in a wide range of values. Resistors implemented by MOS transistors find many useful applications in analog VLS signal and information processing circuits. In continuous-time MOS analog filters high precision RC time-constants are essential, while in many early vision circuits parallel information processing by large-scale active resistive grids are demanding to obtain results in real time, [3], [9]. In such applications, resistive elements are implemented as one-port (floating or nonfloating) active resistor or two-port (as V-I converter) elements and can be implemented as linear or nonlinear (resistive fuse) resistors, [8], [11]. The function of a resistor is often implemented by voltage or current controlled MOS transconductance using some technique to cancel the nonlinearities in a MOS transistor current. A linear NMOS depletion resistor [4] and an enhancement-mode MOS voltage controlled counter part with two transistors are developed in [5]. In [6], a CMOS floating resistor is presented that have linearity within ± 0,04 % achieved through nonlinearity cancellation via current mirrors over an applied voltage range of ± 1V. One CMOS architecture for a floating linear resistor which exploits the square-law MOS transistor model fabricated in 2&m p-well CMOS MOSIS process is published in [7]. Another architecture of floating one- port resistor is presented in the accompanied paper [13].
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This note was uploaded on 02/18/2010 for the course ITK ETF113L07 taught by Professor Popovskiborislav during the Spring '10 term at Pacific.

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E1-1 - Sedma Nacionalna Konferencija so Me|unarodno U~estvo...

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