E3-5 - Sedma Nacionalna Konferencija so Me|unarodno U~estvo...

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ALL-MOS LINEAR RESISTIVE GRIDS FOR SPATIAL VISUAL PROCESSING II: A FLOATING ONE-PORT LINEAR RESISTOR Goce V. Shutinoski 1 1 Ss. Cyril and Methodius University, Department of Electronics, Faculty of EE, Karpos 2 BB, PO box 574, MK-1000 Skopje, Republic of Macedonia, E-mail: [email protected] Abstract – All-MOS floating one-port linear resistive element suitable for both analog and digital signal processing subsystems is presented. It implements enhancement type n-MOS and p- MOS transistors, thus appropriate for CMOS technology. Main static and dynamic circuit characteristics are explored, the possibilities of controlling the variable resistance (tunability) are discussed and simulation results are given. Index terms – MOS, one-port active resistors, resistive grid, floating resistive port 1. INTRODUCTION An active floating one-port linear resistors synthesized by using all MOS transistors are preferable devices in analog circuit design. They occupy smaller area fraction, parasitic capacitance is lower and the resistance value is easily controllable in a wide range. Such IC resistors can be fully designed and fabricated in the same semiconductor processing technology as other signal processing functional blocks and ease design of complex SOC systems, [1], [4], [5], [6]. All-MOS linear resistor is an attractive building device that simulates the function of a one- port real passive resistor and it allows direct replacement of a passive resistor by its all-MOS substitute in versatile applications, [3], [7]. Resistive devices implemented as one-port floating active resistor usually employ some technique to cancel the nonlinearities present in a MOS transistor current. A voltage mirroring used to implement nonfloating linear resistor circuit comprising only three transistors is presented in [3]. A linear NMOS depletion resistor [5] and an enhancement-mode MOS voltage controlled counter part with two transistors are developed in [6]. A CMOS floating resistor [7] have linearity claimed within ± 0,04 % that is achieved through nonlinearity cancellation via current mirrors over an applied voltage range of ± 1V. Another successful CMOS architecture of floating resistor fabricated in 2 µ m p-well CMOS MOSIS process that exploits the square-law transistor operation is published in [8]. In this paper we first review some of the most important approaches and ideas for implementation of all-mos floating resistors focusing on their main characteristics. Next, we propose a mirrored three- transistor floating one-port resistor circuit and investigate its dc and frequency characteristics. The tunability of the resistor and certain modifications of the circuit are also discussed. At last an application of the resistor in early vision resistive grid for retinotopic processing is discussed.
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This note was uploaded on 02/18/2010 for the course ITK ETF113L07 taught by Professor Popovskiborislav during the Spring '10 term at Pacific.

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E3-5 - Sedma Nacionalna Konferencija so Me|unarodno U~estvo...

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