lecture08-review

lecture08-review - ECE252 Microprocessors Fall 2008 Lecture...

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Jie Hu, ECE/NJIT, Fall 2008 ECE252 L08-Review.1 ECE252 Microprocessors Fall 2008 Lecture 08: Midterm #1 Review Jie Hu http://web.njit.edu/~jhu/ece252
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Jie Hu, ECE/NJIT, Fall 2008 ECE252 L08-Review.2 Today’s Lecture Midterm Exam #1 Review Quiz#2, HW#2, HW #3 Sample Exams
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Jie Hu, ECE/NJIT, Fall 2008 ECE252 L08-Review.3 Microprocessor based Systems Parallel I/O Serial I/O Interrupt Circuitry CPU Timing Memory System Bus
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Jie Hu, ECE/NJIT, Fall 2008 ECE252 L08-Review.4 Microprocessor based Systems CPU (central processing unit) microprocessor logic circuitry for communicating with the system bus: data/address bus driver, bus controller Timing unit generates clock signals and is responsible for the proper operation of all system hardware crystal oscillator and timing circuitry Memory stores both program code and data ROM (read-only memory), RAM (random access memory) Interrupt circuitry mechanism for the processor to respond to special external events I/O, peripherals monitor, keyboard, mouse, printer, …
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Jie Hu, ECE/NJIT, Fall 2008 ECE252 L08-Review.5 Microprocessor Operation Reset Fetch Decode Execute Start here at power-on or when a reset signal is received 1.Output inst. address on address bus 2. Read inst. pattern from memory onto data bus 3. Increment inst. pointer (program counter) Determine what type of instruction was fetched 1. If necessary, read data from memory 2. Execute instruction 3. if necessary, write results to memory Repeat this process until power is turned off or the processor is halted.
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Jie Hu, ECE/NJIT, Fall 2008 ECE252 L08-Review.6 68000 Microprocessor Pin Input/Output Signals D 15 –D 0 AS UDS LDS R/W DTACK BG BGACK BR V CC CLK HALT RESET VMA E VPA BERR IPL 2 IPL 1 IPL 0 FC 2 FC 1 FC 0 V CC GND GND 68000 CPU A 23 –A 1 +5V Data bus Address bus Asynchronous bus control Bus arbitration control Interrupt control System control 6800 peripheral control Processor status
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Jie Hu, ECE/NJIT, Fall 2008 ECE252 L08-Review.7 68000 Programming Model Data Register Address Register Program counter Status register 0 31 D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 A7 USP SSP PC SR 0 15 0 31 0 31 23
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This note was uploaded on 02/18/2010 for the course ECET 252 taught by Professor Hu during the Spring '10 term at NJIT.

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lecture08-review - ECE252 Microprocessors Fall 2008 Lecture...

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