July09_Lesson5 - Key Lecture Concepts for CoE225/EE 271...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon
Key Lecture Concepts for CoE225/EE 271 (Mostly Digital Electronics) 1 LESSON 5: Basic Capacitance Concepts for Digital Logic and Memory Circuits; Introduction to the Logic Inverter Circuit Composed of an E-MOST Switch and a DMOST Load. A) Overview of the Microelectronics Industry and the Lesson Objectives Over the last five decades, the electronics industry has continuously improved the technology for manufacturing very dense logic and memory systems at low cost on the surface of a silicon substrate. Fig5.1 shows the improvement in terms of the minimum dimension of a region of material on a silicon wafer (scale in microns on the right) and the number of transistors on a wafer (scale on the right). Much of the improvement is due to the decrease in this minimum dimension. The dimension is indicative of how many devices, and thus logic gates and memory cells, can be packed on the surface of silicon wafer and on pieces of the wafer, e.g. one cm square silicon chips. It also indicates that the components and systems on the chip can operate at higher computer clock frequencies. The integration of many electronic components on a silicon wafer, and the chips that can be made from the wafer, is done completely by machines making and testing the chips. Thus integrated circuit manufacturing has high yield of “good” chips versus the sum of good plus defective ones because human errors are nearly eliminated. As the minimum dimension, and thus the distance between source and drain was made smaller each year, the yield decreased because there is a greater chance of making a defective transistor or interconnection. [The fabrication is typically done in a “class 10 Clean Room” which has less than 10 micron-sized dust particles per cubic foot. These particles can stick on the photo-sensitive polymer, whose exposure by UV light through a metal mask determines the geometry of the devices and metal interconnections, resulting in defects in the circuits.] However, smaller-sized devices meant higher chip performance in terms of lower power consumption per component (but not necessarily per system), greater logic processing speed, larger logic and memory capability etc. Therefore fabrication errors can be tolerated as long as the defective chips are detected. The quality of testing equipment over the years has kept pace with the need to test smaller and faster digital signals because the test equipment was made with state-of-the-art integrated circuits being tested. (smile) Generally speaking the cost of a microelectronics system over the past four decades is due to not only the manufacturing facility referred to as the Fabrication “Fab” Laboratory (surprisingly only 10% or less of the total cost) but the design of the chips (~30 to 40 %), the testing of the reliability of the chips (~30 %) and the materials (~ 20 t0 30%). The ~5 billion dollar Fab Lab built by Intel Corp. in 2007 manufactures MOS circuits with minimum dimensions of 0.043 microns. In 43 nanometers there are about 125 atoms. To justify such a cost,
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 2
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 02/18/2010 for the course ECET 271 taught by Professor Hu during the Spring '05 term at NJIT.

Page1 / 18

July09_Lesson5 - Key Lecture Concepts for CoE225/EE 271...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online