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ECE354 S'09 hw6

# ECE354 S'09 hw6 - the full cycle you have computed in Pb 1...

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NEW JERSEY INSTITUTE OF TECHNOLOGY DEPT. OF ELECTRICAL & COMPUTER ENGINEERING ACADEMIC YEAR 2008-2009 SEMESTER 2 ECE354 DIGITAL TEST HW 6 Refer to the following circuit whenever applicable: A B C D F 1 g 2 g 3 g 4 g 5 g 6 g 7 g 8 g 9 g 10 g 11 g Fig. 1. Circuit for HW6 Fig. 2 The test generator G1 G2 G3 G4 To A To B To C To D S1 S2 S3 Fig. 3 The data compressor From F 1. The LFSR of Fig. 2 is inserted with the seed G1G2G3G4=0001. The LFSR is continuously clocked until the original seed appears again. Compute the states of one full cycle of this LFSR. How many states are traversed in a full cycle (every state is counted only once in this count)? Does this LFSR implement a primitive polynomial? 2. The LFSR of Fig. 2 is used to generate patterns to test the circuit of Fig. 1. The test set is

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Unformatted text preview: the full cycle you have computed in Pb. 1, where the first pattern in the set is the initial 1 seed. The LFSR of Fig. 3 is used to capture the responses of the circuit to this test. The initial seed of this LFSR is S1S2S3=000. Compute the good circuit signature captured in the LFSR of Fig. 3 at the end of the test. 3. If the circuit of Fig. 1 possesses the fault A /0, will the test described in Pb. 2 detect it? 4. If the circuit of Fig. 1 possesses the fault 1 / 7 g , will the test described in Pb. 2 detect it? 5. If the circuit of Fig. 1 possesses the fault 1 / 6 g , will the test described in Pb. 2 detect it? 2...
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