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ECE354 S'09 hw7

# ECE354 S'09 hw7 - (b What is the 1’s count in the...

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NEW JERSEY INSTITUTE OF TECHNOLOGY DEPT. OF ELECTRICAL & COMPUTER ENGINEERING ACADEMIC YEAR 2008-2009 SEMESTER 2 ECE354 DIGITAL TEST HW 7 Refer to the following circuit whenever applicable: A B C D F 1 g 2 g 3 g 4 g 5 g 6 g 7 g 8 g 9 g 10 g 11 g Fig. 1. Circuit for HW7 1. Compute a test pattern for 1 / 3 g using the D-algorithm. 2. Compute a test pattern for 0 / 6 g using the D-algorithm. 3. The circuit is fed with the exhaustive set progressing in the binary count order, i.e. ABCD =0000,0001,0010,0011,…,1110,1111. The output responses are accumulated in a 1’s counter. (a) What is the expected 1’s count for the good circuit?
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Unformatted text preview: (b) What is the 1’s count in the presence of 1 / 9 g ? Is the fault detected by this scheme? 4. The circuit is fed with the exhaustive set progressing in the binary count order, i.e. ABCD =0000,0001,0010,0011,…,1110,1111. The output responses are accumulated in a transition counter. (a) What is the transition count for the good circuit? (b) What is the transition count in the presence of 1 / 9 g ? Is the fault detected by this scheme? 5. Repeat Pb. 4 if the input vector set is ABCD =0000,0001,0010,0101,0110,1001,1010. 1...
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