352-post3 - ECE/CS352 DemoSection602 Fall2009 Experiment3...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
ECE/CS 352 Demo Section 602 Fall 2009 Experiment 3  Post-demo Report Submitted by: Michael Frederick Instructor: Meng Shi Page 1 of 3
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Description of Applied Homework   I examined the differences between latches and flip flops using the circuits that I  created and another circuit which was provided to me.  I loaded all of the circuits onto  the FPGA board and observed values using the board as well as the oscillator. Answers to Assignment Questions 1. GPIO_0[0] is positive edge triggered and it is up for one cycle of GPIO_0[4]  (CLOCK_27) at a time. Yes, this is expected. 2. GPIO_0[1] is the output of the latch. Every time that GPIO_0[4] is equal to zero,  GPIO_0[1] has switched values.  When GPIO_0[4] is positive, GPIO_0[1] is volatile (it  switches values quickly and repeatedly).  The output of GPIO_0[1] is the same as the  output of GPIO_0[0] except when the clock is set.  The inconsistency in the value of 
Background image of page 2
Image of page 3
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

Page1 / 3

352-post3 - ECE/CS352 DemoSection602 Fall2009 Experiment3...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online